1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mtriple=hexagon < %s | FileCheck %s 3; 4; Check if we generate rounding-asr instruction. It is equivalent to 5; Rd = ((Rs >> #u) +1) >> 1. 6target triple = "hexagon" 7 8; Function Attrs: nounwind 9define i32 @f0(i32 %a0) #0 { 10; CHECK-LABEL: f0: 11; CHECK: // %bb.0: // %b0 12; CHECK-NEXT: { 13; CHECK-NEXT: r0 = asr(r0,#10):rnd 14; CHECK-NEXT: r1 = r0 15; CHECK-NEXT: r29 = add(r29,#-8) 16; CHECK-NEXT: } 17; CHECK-NEXT: { 18; CHECK-NEXT: r29 = add(r29,#8) 19; CHECK-NEXT: jumpr r31 20; CHECK-NEXT: memw(r29+#4) = r1 21; CHECK-NEXT: } 22b0: 23 %v0 = alloca i32, align 4 24 store i32 %a0, ptr %v0, align 4 25 %v1 = load i32, ptr %v0, align 4 26 %v2 = ashr i32 %v1, 10 27 %v3 = add nsw i32 %v2, 1 28 %v4 = ashr i32 %v3, 1 29 ret i32 %v4 30} 31 32; Function Attrs: nounwind 33define i64 @f1(i64 %a0) #0 { 34; CHECK-LABEL: f1: 35; CHECK: // %bb.0: // %b0 36; CHECK-NEXT: { 37; CHECK-NEXT: r1:0 = asr(r1:0,#17):rnd 38; CHECK-NEXT: r3:2 = combine(r1,r0) 39; CHECK-NEXT: r29 = add(r29,#-8) 40; CHECK-NEXT: } 41; CHECK-NEXT: { 42; CHECK-NEXT: r29 = add(r29,#8) 43; CHECK-NEXT: jumpr r31 44; CHECK-NEXT: memd(r29+#0) = r3:2 45; CHECK-NEXT: } 46b0: 47 %v0 = alloca i64, align 8 48 store i64 %a0, ptr %v0, align 8 49 %v1 = load i64, ptr %v0, align 8 50 %v2 = ashr i64 %v1, 17 51 %v3 = add nsw i64 %v2, 1 52 %v4 = ashr i64 %v3, 1 53 ret i64 %v4 54} 55 56attributes #0 = { nounwind } 57