1; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s 2 3; CHECK-NOT: [[REG0:(r[0-9]+)]] = memw([[REG0:(r[0-9]+)]]<<#2+##state-4) 4 5%s.0 = type { i16, [10 x ptr] } 6%s.1 = type { %s.2, i16, i16 } 7%s.2 = type { i8, [15 x %s.3], [18 x %s.4], %s.5, i16 } 8%s.3 = type { %s.5, ptr, ptr, i16, i8, i8, [3 x ptr], [3 x ptr], [3 x ptr] } 9%s.4 = type { %s.5, ptr, i8, i16, i8 } 10%s.5 = type { ptr, ptr } 11%s.6 = type { i8, i8 } 12 13@g0 = common global %s.0 zeroinitializer, align 4 14 15; Function Attrs: nounwind optsize 16define void @f0(ptr nocapture readonly %a0) local_unnamed_addr #0 { 17b0: 18 %v1 = getelementptr %s.6, ptr %a0, i32 0, i32 1 19 %v2 = load i8, ptr %v1, align 1 20 %v3 = zext i8 %v2 to i32 21 %v4 = add nsw i32 %v3, -1 22 %v5 = getelementptr %s.0, ptr @g0, i32 0, i32 1 23 %v6 = getelementptr [10 x ptr], ptr %v5, i32 0, i32 %v4 24 %v7 = load ptr, ptr %v6, align 4 25 %v8 = icmp eq ptr %v7, null 26 br i1 %v8, label %b4, label %b1 27 28b1: ; preds = %b0 29 %v11 = load i8, ptr %v7, align 4 30 %v12 = icmp eq i8 %v11, %v2 31 br i1 %v12, label %b2, label %b4 32 33b2: ; preds = %b1 34 tail call void @f1(ptr nonnull %v7) #2 35 %v14 = getelementptr %s.6, ptr %a0, i32 0, i32 1 36 %v15 = load i8, ptr %v14, align 1 37 %v16 = zext i8 %v15 to i32 38 %v17 = add nsw i32 %v16, -1 39 %v18 = getelementptr [10 x ptr], ptr %v5, i32 0, i32 %v17 40 %v19 = load ptr, ptr %v18, align 4 41 %v20 = icmp eq ptr %v19, null 42 br i1 %v20, label %b4, label %b3 43 44b3: ; preds = %b2 45 %v21 = getelementptr %s.1, ptr %v19, i32 0, i32 0, i32 3 46 tail call void @f2(ptr %v21) #2 47 store ptr null, ptr %v18, align 4 48 br label %b4 49 50b4: ; preds = %b3, %b2, %b1, %b0 51 ret void 52} 53 54; Function Attrs: optsize 55declare void @f1(ptr) #1 56 57; Function Attrs: optsize 58declare void @f2(ptr) #1 59 60attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } 61attributes #1 = { optsize "target-cpu"="hexagonv60" "target-features"="+hvx" } 62attributes #2 = { nounwind } 63