xref: /llvm-project/llvm/test/CodeGen/Hexagon/addh.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; RUN: llc -mtriple=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s
3; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}})
4
5define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone {
6entry:
7  %conv.i = zext i16 %arg1 to i32
8  %conv1.i = zext i16 %arg2 to i32
9  %sub.i = add nsw i32 %conv.i, %conv1.i
10  %sext.i = shl i32 %sub.i, 16
11  %cmp.i = icmp slt i32 %sext.i, 65536
12  %0 = ashr exact i32 %sext.i, 16
13  %conv7.i = select i1 %cmp.i, i32 1, i32 %0
14  %cmp8.i = icmp sgt i32 %conv7.i, 4
15  %conv7.op.i = add i32 %conv7.i, 65535
16  %shl = shl i64 %arg0, 2
17  %.mask = and i32 %conv7.op.i, 65535
18  %1 = zext i32 %.mask to i64
19  %conv = select i1 %cmp8.i, i64 3, i64 %1
20  %or = or i64 %conv, %shl
21  ret i64 %or
22}
23