1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -S -dxil-intrinsic-expansion -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s 3 4 5define noundef i32 @sign_half(half noundef %a) { 6; CHECK-LABEL: define noundef i32 @sign_half( 7; CHECK-SAME: half noundef [[A:%.*]]) { 8; CHECK-NEXT: [[ENTRY:.*:]] 9; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt half 0xH0000, [[A]] 10; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt half [[A]], 0xH0000 11; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP0]] to i32 12; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP1]] to i32 13; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] 14; CHECK-NEXT: ret i32 [[TMP4]] 15; 16entry: 17 %elt.sign = call i32 @llvm.dx.sign.f16(half %a) 18 ret i32 %elt.sign 19} 20 21define noundef i32 @sign_float(float noundef %a) { 22; CHECK-LABEL: define noundef i32 @sign_float( 23; CHECK-SAME: float noundef [[A:%.*]]) { 24; CHECK-NEXT: [[ENTRY:.*:]] 25; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt float 0.000000e+00, [[A]] 26; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt float [[A]], 0.000000e+00 27; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP0]] to i32 28; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP1]] to i32 29; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] 30; CHECK-NEXT: ret i32 [[TMP4]] 31; 32entry: 33 %elt.sign = call i32 @llvm.dx.sign.f32(float %a) 34 ret i32 %elt.sign 35} 36 37define noundef i32 @sign_double(double noundef %a) { 38; CHECK-LABEL: define noundef i32 @sign_double( 39; CHECK-SAME: double noundef [[A:%.*]]) { 40; CHECK-NEXT: [[ENTRY:.*:]] 41; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt double 0.000000e+00, [[A]] 42; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt double [[A]], 0.000000e+00 43; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP0]] to i32 44; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP1]] to i32 45; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] 46; CHECK-NEXT: ret i32 [[TMP4]] 47; 48entry: 49 %elt.sign = call i32 @llvm.dx.sign.f64(double %a) 50 ret i32 %elt.sign 51} 52 53define noundef i32 @sign_i16(i16 noundef %a) { 54; CHECK-LABEL: define noundef i32 @sign_i16( 55; CHECK-SAME: i16 noundef [[A:%.*]]) { 56; CHECK-NEXT: [[ENTRY:.*:]] 57; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i16 0, [[A]] 58; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i16 [[A]], 0 59; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP0]] to i32 60; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP1]] to i32 61; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] 62; CHECK-NEXT: ret i32 [[TMP4]] 63; 64entry: 65 %elt.sign = call i32 @llvm.dx.sign.i16(i16 %a) 66 ret i32 %elt.sign 67} 68 69define noundef i32 @sign_i32(i32 noundef %a) { 70; CHECK-LABEL: define noundef i32 @sign_i32( 71; CHECK-SAME: i32 noundef [[A:%.*]]) { 72; CHECK-NEXT: [[ENTRY:.*:]] 73; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i32 0, [[A]] 74; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A]], 0 75; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP0]] to i32 76; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP1]] to i32 77; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] 78; CHECK-NEXT: ret i32 [[TMP4]] 79; 80entry: 81 %elt.sign = call i32 @llvm.dx.sign.i32(i32 %a) 82 ret i32 %elt.sign 83} 84 85define noundef i32 @sign_i64(i64 noundef %a) { 86; CHECK-LABEL: define noundef i32 @sign_i64( 87; CHECK-SAME: i64 noundef [[A:%.*]]) { 88; CHECK-NEXT: [[ENTRY:.*:]] 89; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i64 0, [[A]] 90; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i64 [[A]], 0 91; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP0]] to i32 92; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP1]] to i32 93; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]] 94; CHECK-NEXT: ret i32 [[TMP4]] 95; 96entry: 97 %elt.sign = call i32 @llvm.dx.sign.i64(i64 %a) 98 ret i32 %elt.sign 99} 100 101define noundef <4 x i32> @sign_half_vector(<4 x half> noundef %a) { 102; CHECK-LABEL: define noundef <4 x i32> @sign_half_vector( 103; CHECK-SAME: <4 x half> noundef [[A:%.*]]) { 104; CHECK-NEXT: [[ENTRY:.*:]] 105; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x half> zeroinitializer, [[A]] 106; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt <4 x half> [[A]], zeroinitializer 107; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP0]] to <4 x i32> 108; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> 109; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[TMP2]], [[TMP3]] 110; CHECK-NEXT: ret <4 x i32> [[TMP4]] 111; 112entry: 113 %elt.sign = call <4 x i32> @llvm.dx.sign.v4f16(<4 x half> %a) 114 ret <4 x i32> %elt.sign 115} 116 117define noundef <4 x i32> @sign_float_vector(<4 x float> noundef %a) { 118; CHECK-LABEL: define noundef <4 x i32> @sign_float_vector( 119; CHECK-SAME: <4 x float> noundef [[A:%.*]]) { 120; CHECK-NEXT: [[ENTRY:.*:]] 121; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> zeroinitializer, [[A]] 122; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt <4 x float> [[A]], zeroinitializer 123; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP0]] to <4 x i32> 124; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> 125; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[TMP2]], [[TMP3]] 126; CHECK-NEXT: ret <4 x i32> [[TMP4]] 127; 128entry: 129 %elt.sign = call <4 x i32> @llvm.dx.sign.v4f32(<4 x float> %a) 130 ret <4 x i32> %elt.sign 131} 132 133define noundef <4 x i32> @sign_double_vector(<4 x double> noundef %a) { 134; CHECK-LABEL: define noundef <4 x i32> @sign_double_vector( 135; CHECK-SAME: <4 x double> noundef [[A:%.*]]) { 136; CHECK-NEXT: [[ENTRY:.*:]] 137; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x double> zeroinitializer, [[A]] 138; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt <4 x double> [[A]], zeroinitializer 139; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP0]] to <4 x i32> 140; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> 141; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[TMP2]], [[TMP3]] 142; CHECK-NEXT: ret <4 x i32> [[TMP4]] 143; 144entry: 145 %elt.sign = call <4 x i32> @llvm.dx.sign.v4f64(<4 x double> %a) 146 ret <4 x i32> %elt.sign 147} 148 149define noundef <4 x i32> @sign_i16_vector(<4 x i16> noundef %a) { 150; CHECK-LABEL: define noundef <4 x i32> @sign_i16_vector( 151; CHECK-SAME: <4 x i16> noundef [[A:%.*]]) { 152; CHECK-NEXT: [[ENTRY:.*:]] 153; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i16> zeroinitializer, [[A]] 154; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i16> [[A]], zeroinitializer 155; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP0]] to <4 x i32> 156; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> 157; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[TMP2]], [[TMP3]] 158; CHECK-NEXT: ret <4 x i32> [[TMP4]] 159; 160entry: 161 %elt.sign = call <4 x i32> @llvm.dx.sign.v4i16(<4 x i16> %a) 162 ret <4 x i32> %elt.sign 163} 164 165define noundef <4 x i32> @sign_i32_vector(<4 x i32> noundef %a) { 166; CHECK-LABEL: define noundef <4 x i32> @sign_i32_vector( 167; CHECK-SAME: <4 x i32> noundef [[A:%.*]]) { 168; CHECK-NEXT: [[ENTRY:.*:]] 169; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> zeroinitializer, [[A]] 170; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[A]], zeroinitializer 171; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP0]] to <4 x i32> 172; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> 173; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[TMP2]], [[TMP3]] 174; CHECK-NEXT: ret <4 x i32> [[TMP4]] 175; 176entry: 177 %elt.sign = call <4 x i32> @llvm.dx.sign.v4i32(<4 x i32> %a) 178 ret <4 x i32> %elt.sign 179} 180 181define noundef <4 x i32> @sign_i64_vector(<4 x i64> noundef %a) { 182; CHECK-LABEL: define noundef <4 x i32> @sign_i64_vector( 183; CHECK-SAME: <4 x i64> noundef [[A:%.*]]) { 184; CHECK-NEXT: [[ENTRY:.*:]] 185; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i64> zeroinitializer, [[A]] 186; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i64> [[A]], zeroinitializer 187; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP0]] to <4 x i32> 188; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> 189; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[TMP2]], [[TMP3]] 190; CHECK-NEXT: ret <4 x i32> [[TMP4]] 191; 192entry: 193 %elt.sign = call <4 x i32> @llvm.dx.sign.v4i64(<4 x i64> %a) 194 ret <4 x i32> %elt.sign 195} 196 197 198declare i32 @llvm.dx.sign.f16(half) 199declare i32 @llvm.dx.sign.f32(float) 200declare i32 @llvm.dx.sign.f64(double) 201 202declare i32 @llvm.dx.sign.i16(i16) 203declare i32 @llvm.dx.sign.i32(i32) 204declare i32 @llvm.dx.sign.i64(i64) 205 206declare <4 x i32> @llvm.dx.sign.v4f16(<4 x half>) 207declare <4 x i32> @llvm.dx.sign.v4f32(<4 x float>) 208declare <4 x i32> @llvm.dx.sign.v4f64(<4 x double>) 209 210declare <4 x i32> @llvm.dx.sign.v4i16(<4 x i16>) 211declare <4 x i32> @llvm.dx.sign.v4i32(<4 x i32>) 212declare <4 x i32> @llvm.dx.sign.v4i64(<4 x i64>) 213