1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=csky -mattr=+fpuv2_sf,+fpuv2_df,+hard-float -float-abi=hard -verify-machineinstrs -csky-no-aliases < %s \ 3; RUN: | FileCheck -check-prefix=CSKYIFD %s 4 5; These test that we can use both the architectural names (r*) and the ABI names 6; (a*, l* etc) to refer to registers in inline asm constraint lists. In each 7; case, the named register should be used for the source register of the `addi`. 8; 9; The inline assembly will, by default, contain the ABI names for the registers. 10; 11; Parenthesised registers in comments are the other aliases for this register. 12 13define double @explicit_register_fr0_d(double %a, double %b) nounwind { 14; CSKYIFD-LABEL: explicit_register_fr0_d: 15; CSKYIFD: # %bb.0: 16; CSKYIFD-NEXT: subi16 sp, sp, 4 17; CSKYIFD-NEXT: fmovd vr0, vr1 18; CSKYIFD-NEXT: #APP 19; CSKYIFD-NEXT: faddd vr0, vr0, vr0 20; CSKYIFD-NEXT: #NO_APP 21; CSKYIFD-NEXT: addi16 sp, sp, 4 22; CSKYIFD-NEXT: rts16 23 %1 = tail call double asm "faddd $0, $1, $2", "=v,{fr0},{fr0}"(double %a, double %b) 24 ret double %1 25} 26 27define double @explicit_register_vr0_d(double %a, double %b) nounwind { 28; CSKYIFD-LABEL: explicit_register_vr0_d: 29; CSKYIFD: # %bb.0: 30; CSKYIFD-NEXT: subi16 sp, sp, 4 31; CSKYIFD-NEXT: fmovd vr0, vr1 32; CSKYIFD-NEXT: #APP 33; CSKYIFD-NEXT: faddd vr0, vr0, vr0 34; CSKYIFD-NEXT: #NO_APP 35; CSKYIFD-NEXT: addi16 sp, sp, 4 36; CSKYIFD-NEXT: rts16 37 %1 = tail call double asm "faddd $0, $1, $2", "=v,{vr0},{vr0}"(double %a, double %b) 38 ret double %1 39} 40 41define float @explicit_register_fr0_s(float %a, float %b) nounwind { 42; CSKYIFD-LABEL: explicit_register_fr0_s: 43; CSKYIFD: # %bb.0: 44; CSKYIFD-NEXT: subi16 sp, sp, 4 45; CSKYIFD-NEXT: fstod vr0, vr1 46; CSKYIFD-NEXT: #APP 47; CSKYIFD-NEXT: fadds vr0, vr0, vr0 48; CSKYIFD-NEXT: #NO_APP 49; CSKYIFD-NEXT: addi16 sp, sp, 4 50; CSKYIFD-NEXT: rts16 51 %1 = tail call float asm "fadds $0, $1, $2", "=v,{fr0},{fr0}"(float %a, float %b) 52 ret float %1 53} 54 55define float @explicit_register_vr0_s(float %a, float %b) nounwind { 56; CSKYIFD-LABEL: explicit_register_vr0_s: 57; CSKYIFD: # %bb.0: 58; CSKYIFD-NEXT: subi16 sp, sp, 4 59; CSKYIFD-NEXT: fstod vr0, vr1 60; CSKYIFD-NEXT: #APP 61; CSKYIFD-NEXT: fadds vr0, vr0, vr0 62; CSKYIFD-NEXT: #NO_APP 63; CSKYIFD-NEXT: addi16 sp, sp, 4 64; CSKYIFD-NEXT: rts16 65 %1 = tail call float asm "fadds $0, $1, $2", "=v,{vr0},{vr0}"(float %a, float %b) 66 ret float %1 67} 68