1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 3; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF 4; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2 5 6;ueq 7define i1 @fcmpRR_ueq(float %x, float %y) { 8; 9; CHECK-SF-LABEL: fcmpRR_ueq: 10; CHECK-SF: # %bb.0: # %entry 11; CHECK-SF-NEXT: fcmpuos vr1, vr0 12; CHECK-SF-NEXT: mvc32 a0 13; CHECK-SF-NEXT: fcmpnes vr1, vr0 14; CHECK-SF-NEXT: mvcv16 a1 15; CHECK-SF-NEXT: or16 a0, a1 16; CHECK-SF-NEXT: rts16 17; 18; CHECK-SF2-LABEL: fcmpRR_ueq: 19; CHECK-SF2: # %bb.0: # %entry 20; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0 21; CHECK-SF2-NEXT: mvc32 a0 22; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0 23; CHECK-SF2-NEXT: mvcv16 a1 24; CHECK-SF2-NEXT: or16 a0, a1 25; CHECK-SF2-NEXT: rts16 26entry: 27 %fcmp = fcmp ueq float %y, %x 28 ret i1 %fcmp 29} 30 31define i1 @fcmpRI_ueq(float %x) { 32; 33; CHECK-SF-LABEL: fcmpRI_ueq: 34; CHECK-SF: # %bb.0: # %entry 35; CHECK-SF-NEXT: movih32 a0, 49440 36; CHECK-SF-NEXT: fmtvrl vr1, a0 37; CHECK-SF-NEXT: fcmpnes vr0, vr1 38; CHECK-SF-NEXT: mvcv16 a0 39; CHECK-SF-NEXT: fcmpuos vr0, vr0 40; CHECK-SF-NEXT: mvc32 a1 41; CHECK-SF-NEXT: or16 a0, a1 42; CHECK-SF-NEXT: rts16 43; 44; CHECK-SF2-LABEL: fcmpRI_ueq: 45; CHECK-SF2: # %bb.0: # %entry 46; CHECK-SF2-NEXT: movih32 a0, 49440 47; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 48; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1 49; CHECK-SF2-NEXT: mvcv16 a0 50; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0 51; CHECK-SF2-NEXT: mvc32 a1 52; CHECK-SF2-NEXT: or16 a0, a1 53; CHECK-SF2-NEXT: rts16 54entry: 55 %fcmp = fcmp ueq float %x, -10.0 56 ret i1 %fcmp 57} 58 59define i1 @fcmpRI_X_ueq(float %x) { 60; 61; CHECK-SF-LABEL: fcmpRI_X_ueq: 62; CHECK-SF: # %bb.0: # %entry 63; CHECK-SF-NEXT: fcmpuos vr0, vr0 64; CHECK-SF-NEXT: mvc32 a0 65; CHECK-SF-NEXT: fcmpznes vr0 66; CHECK-SF-NEXT: mvcv16 a1 67; CHECK-SF-NEXT: or16 a0, a1 68; CHECK-SF-NEXT: rts16 69; 70; CHECK-SF2-LABEL: fcmpRI_X_ueq: 71; CHECK-SF2: # %bb.0: # %entry 72; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0 73; CHECK-SF2-NEXT: mvc32 a0 74; CHECK-SF2-NEXT: fcmpnez.32 vr0 75; CHECK-SF2-NEXT: mvcv16 a1 76; CHECK-SF2-NEXT: or16 a0, a1 77; CHECK-SF2-NEXT: rts16 78entry: 79 %fcmp = fcmp ueq float %x, 0.0 80 ret i1 %fcmp 81} 82 83 84;une 85define i1 @fcmpRR_une(float %x, float %y) { 86; 87; CHECK-SF-LABEL: fcmpRR_une: 88; CHECK-SF: # %bb.0: # %entry 89; CHECK-SF-NEXT: fcmpnes vr1, vr0 90; CHECK-SF-NEXT: mvc32 a0 91; CHECK-SF-NEXT: rts16 92; 93; CHECK-SF2-LABEL: fcmpRR_une: 94; CHECK-SF2: # %bb.0: # %entry 95; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0 96; CHECK-SF2-NEXT: mvc32 a0 97; CHECK-SF2-NEXT: rts16 98entry: 99 %fcmp = fcmp une float %y, %x 100 ret i1 %fcmp 101} 102 103define i1 @fcmpRI_une(float %x) { 104; 105; CHECK-SF-LABEL: fcmpRI_une: 106; CHECK-SF: # %bb.0: # %entry 107; CHECK-SF-NEXT: movih32 a0, 49440 108; CHECK-SF-NEXT: fmtvrl vr1, a0 109; CHECK-SF-NEXT: fcmpnes vr0, vr1 110; CHECK-SF-NEXT: mvc32 a0 111; CHECK-SF-NEXT: rts16 112; 113; CHECK-SF2-LABEL: fcmpRI_une: 114; CHECK-SF2: # %bb.0: # %entry 115; CHECK-SF2-NEXT: movih32 a0, 49440 116; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 117; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1 118; CHECK-SF2-NEXT: mvc32 a0 119; CHECK-SF2-NEXT: rts16 120entry: 121 %fcmp = fcmp une float %x, -10.0 122 ret i1 %fcmp 123} 124 125define i1 @fcmpRI_X_une(float %x) { 126; 127; CHECK-SF-LABEL: fcmpRI_X_une: 128; CHECK-SF: # %bb.0: # %entry 129; CHECK-SF-NEXT: fcmpznes vr0 130; CHECK-SF-NEXT: mvc32 a0 131; CHECK-SF-NEXT: rts16 132; 133; CHECK-SF2-LABEL: fcmpRI_X_une: 134; CHECK-SF2: # %bb.0: # %entry 135; CHECK-SF2-NEXT: fcmpnez.32 vr0 136; CHECK-SF2-NEXT: mvc32 a0 137; CHECK-SF2-NEXT: rts16 138entry: 139 %fcmp = fcmp une float %x, 0.0 140 ret i1 %fcmp 141} 142 143 144;ugt 145define i1 @fcmpRR_ugt(float %x, float %y) { 146; 147; CHECK-SF-LABEL: fcmpRR_ugt: 148; CHECK-SF: # %bb.0: # %entry 149; CHECK-SF-NEXT: fcmphss vr0, vr1 150; CHECK-SF-NEXT: mvc32 a0 151; CHECK-SF-NEXT: xori32 a0, a0, 1 152; CHECK-SF-NEXT: rts16 153; 154; CHECK-SF2-LABEL: fcmpRR_ugt: 155; CHECK-SF2: # %bb.0: # %entry 156; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1 157; CHECK-SF2-NEXT: mvc32 a0 158; CHECK-SF2-NEXT: xori32 a0, a0, 1 159; CHECK-SF2-NEXT: rts16 160entry: 161 %fcmp = fcmp ugt float %y, %x 162 ret i1 %fcmp 163} 164 165define i1 @fcmpRI_ugt(float %x) { 166; 167; CHECK-SF-LABEL: fcmpRI_ugt: 168; CHECK-SF: # %bb.0: # %entry 169; CHECK-SF-NEXT: movih32 a0, 49440 170; CHECK-SF-NEXT: fmtvrl vr1, a0 171; CHECK-SF-NEXT: fcmphss vr1, vr0 172; CHECK-SF-NEXT: mvc32 a0 173; CHECK-SF-NEXT: xori32 a0, a0, 1 174; CHECK-SF-NEXT: rts16 175; 176; CHECK-SF2-LABEL: fcmpRI_ugt: 177; CHECK-SF2: # %bb.0: # %entry 178; CHECK-SF2-NEXT: movih32 a0, 49440 179; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 180; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0 181; CHECK-SF2-NEXT: mvc32 a0 182; CHECK-SF2-NEXT: xori32 a0, a0, 1 183; CHECK-SF2-NEXT: rts16 184entry: 185 %fcmp = fcmp ugt float %x, -10.0 186 ret i1 %fcmp 187} 188 189define i1 @fcmpRI_X_ugt(float %x) { 190; 191; CHECK-SF-LABEL: fcmpRI_X_ugt: 192; CHECK-SF: # %bb.0: # %entry 193; CHECK-SF-NEXT: fcmpzlss vr0 194; CHECK-SF-NEXT: mvc32 a0 195; CHECK-SF-NEXT: xori32 a0, a0, 1 196; CHECK-SF-NEXT: rts16 197; 198; CHECK-SF2-LABEL: fcmpRI_X_ugt: 199; CHECK-SF2: # %bb.0: # %entry 200; CHECK-SF2-NEXT: fcmplsz.32 vr0 201; CHECK-SF2-NEXT: mvc32 a0 202; CHECK-SF2-NEXT: xori32 a0, a0, 1 203; CHECK-SF2-NEXT: rts16 204entry: 205 %fcmp = fcmp ugt float %x, 0.0 206 ret i1 %fcmp 207} 208 209 210;uge 211define i1 @fcmpRR_uge(float %x, float %y) { 212; 213; CHECK-SF-LABEL: fcmpRR_uge: 214; CHECK-SF: # %bb.0: # %entry 215; CHECK-SF-NEXT: fcmplts vr1, vr0 216; CHECK-SF-NEXT: mvc32 a0 217; CHECK-SF-NEXT: xori32 a0, a0, 1 218; CHECK-SF-NEXT: rts16 219; 220; CHECK-SF2-LABEL: fcmpRR_uge: 221; CHECK-SF2: # %bb.0: # %entry 222; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0 223; CHECK-SF2-NEXT: mvc32 a0 224; CHECK-SF2-NEXT: xori32 a0, a0, 1 225; CHECK-SF2-NEXT: rts16 226entry: 227 %fcmp = fcmp uge float %y, %x 228 ret i1 %fcmp 229} 230 231define i1 @fcmpRI_uge(float %x) { 232; 233; CHECK-SF-LABEL: fcmpRI_uge: 234; CHECK-SF: # %bb.0: # %entry 235; CHECK-SF-NEXT: movih32 a0, 49440 236; CHECK-SF-NEXT: fmtvrl vr1, a0 237; CHECK-SF-NEXT: fcmplts vr0, vr1 238; CHECK-SF-NEXT: mvc32 a0 239; CHECK-SF-NEXT: xori32 a0, a0, 1 240; CHECK-SF-NEXT: rts16 241; 242; CHECK-SF2-LABEL: fcmpRI_uge: 243; CHECK-SF2: # %bb.0: # %entry 244; CHECK-SF2-NEXT: movih32 a0, 49440 245; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 246; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1 247; CHECK-SF2-NEXT: mvc32 a0 248; CHECK-SF2-NEXT: xori32 a0, a0, 1 249; CHECK-SF2-NEXT: rts16 250entry: 251 %fcmp = fcmp uge float %x, -10.0 252 ret i1 %fcmp 253} 254 255define i1 @fcmpRI_X_uge(float %x) { 256; 257; CHECK-SF-LABEL: fcmpRI_X_uge: 258; CHECK-SF: # %bb.0: # %entry 259; CHECK-SF-NEXT: fcmpzhss vr0 260; CHECK-SF-NEXT: mvcv16 a0 261; CHECK-SF-NEXT: xori32 a0, a0, 1 262; CHECK-SF-NEXT: rts16 263; 264; CHECK-SF2-LABEL: fcmpRI_X_uge: 265; CHECK-SF2: # %bb.0: # %entry 266; CHECK-SF2-NEXT: fcmpltz.32 vr0 267; CHECK-SF2-NEXT: mvc32 a0 268; CHECK-SF2-NEXT: xori32 a0, a0, 1 269; CHECK-SF2-NEXT: rts16 270entry: 271 %fcmp = fcmp uge float %x, 0.0 272 ret i1 %fcmp 273} 274 275;ult 276define i1 @fcmpRR_ult(float %x, float %y) { 277; 278; CHECK-SF-LABEL: fcmpRR_ult: 279; CHECK-SF: # %bb.0: # %entry 280; CHECK-SF-NEXT: fcmphss vr1, vr0 281; CHECK-SF-NEXT: mvc32 a0 282; CHECK-SF-NEXT: xori32 a0, a0, 1 283; CHECK-SF-NEXT: rts16 284; 285; CHECK-SF2-LABEL: fcmpRR_ult: 286; CHECK-SF2: # %bb.0: # %entry 287; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0 288; CHECK-SF2-NEXT: mvc32 a0 289; CHECK-SF2-NEXT: xori32 a0, a0, 1 290; CHECK-SF2-NEXT: rts16 291entry: 292 %fcmp = fcmp ult float %y, %x 293 ret i1 %fcmp 294} 295 296define i1 @fcmpRI_ult(float %x) { 297; 298; CHECK-SF-LABEL: fcmpRI_ult: 299; CHECK-SF: # %bb.0: # %entry 300; CHECK-SF-NEXT: movih32 a0, 49440 301; CHECK-SF-NEXT: fmtvrl vr1, a0 302; CHECK-SF-NEXT: fcmphss vr0, vr1 303; CHECK-SF-NEXT: mvc32 a0 304; CHECK-SF-NEXT: xori32 a0, a0, 1 305; CHECK-SF-NEXT: rts16 306; 307; CHECK-SF2-LABEL: fcmpRI_ult: 308; CHECK-SF2: # %bb.0: # %entry 309; CHECK-SF2-NEXT: movih32 a0, 49440 310; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 311; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1 312; CHECK-SF2-NEXT: mvc32 a0 313; CHECK-SF2-NEXT: xori32 a0, a0, 1 314; CHECK-SF2-NEXT: rts16 315entry: 316 %fcmp = fcmp ult float %x, -10.0 317 ret i1 %fcmp 318} 319 320define i1 @fcmpRI_X_ult(float %x) { 321; 322; CHECK-SF-LABEL: fcmpRI_X_ult: 323; CHECK-SF: # %bb.0: # %entry 324; CHECK-SF-NEXT: fcmpzhss vr0 325; CHECK-SF-NEXT: mvc32 a0 326; CHECK-SF-NEXT: xori32 a0, a0, 1 327; CHECK-SF-NEXT: rts16 328; 329; CHECK-SF2-LABEL: fcmpRI_X_ult: 330; CHECK-SF2: # %bb.0: # %entry 331; CHECK-SF2-NEXT: fcmphsz.32 vr0 332; CHECK-SF2-NEXT: mvc32 a0 333; CHECK-SF2-NEXT: xori32 a0, a0, 1 334; CHECK-SF2-NEXT: rts16 335entry: 336 %fcmp = fcmp ult float %x, 0.0 337 ret i1 %fcmp 338} 339 340 341;ule 342define i1 @fcmpRR_ule(float %x, float %y) { 343; 344; CHECK-SF-LABEL: fcmpRR_ule: 345; CHECK-SF: # %bb.0: # %entry 346; CHECK-SF-NEXT: fcmplts vr0, vr1 347; CHECK-SF-NEXT: mvc32 a0 348; CHECK-SF-NEXT: xori32 a0, a0, 1 349; CHECK-SF-NEXT: rts16 350; 351; CHECK-SF2-LABEL: fcmpRR_ule: 352; CHECK-SF2: # %bb.0: # %entry 353; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1 354; CHECK-SF2-NEXT: mvc32 a0 355; CHECK-SF2-NEXT: xori32 a0, a0, 1 356; CHECK-SF2-NEXT: rts16 357entry: 358 %fcmp = fcmp ule float %y, %x 359 ret i1 %fcmp 360} 361 362define i1 @fcmpRI_ule(float %x) { 363; 364; CHECK-SF-LABEL: fcmpRI_ule: 365; CHECK-SF: # %bb.0: # %entry 366; CHECK-SF-NEXT: movih32 a0, 49440 367; CHECK-SF-NEXT: fmtvrl vr1, a0 368; CHECK-SF-NEXT: fcmplts vr1, vr0 369; CHECK-SF-NEXT: mvc32 a0 370; CHECK-SF-NEXT: xori32 a0, a0, 1 371; CHECK-SF-NEXT: rts16 372; 373; CHECK-SF2-LABEL: fcmpRI_ule: 374; CHECK-SF2: # %bb.0: # %entry 375; CHECK-SF2-NEXT: movih32 a0, 49440 376; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 377; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0 378; CHECK-SF2-NEXT: mvc32 a0 379; CHECK-SF2-NEXT: xori32 a0, a0, 1 380; CHECK-SF2-NEXT: rts16 381entry: 382 %fcmp = fcmp ule float %x, -10.0 383 ret i1 %fcmp 384} 385 386define i1 @fcmpRI_X_ule(float %x) { 387; 388; CHECK-SF-LABEL: fcmpRI_X_ule: 389; CHECK-SF: # %bb.0: # %entry 390; CHECK-SF-NEXT: fcmpzlss vr0 391; CHECK-SF-NEXT: mvcv16 a0 392; CHECK-SF-NEXT: xori32 a0, a0, 1 393; CHECK-SF-NEXT: rts16 394; 395; CHECK-SF2-LABEL: fcmpRI_X_ule: 396; CHECK-SF2: # %bb.0: # %entry 397; CHECK-SF2-NEXT: fcmphz.32 vr0 398; CHECK-SF2-NEXT: mvc32 a0 399; CHECK-SF2-NEXT: xori32 a0, a0, 1 400; CHECK-SF2-NEXT: rts16 401entry: 402 %fcmp = fcmp ule float %x, 0.0 403 ret i1 %fcmp 404} 405 406 407;ogt 408define i1 @fcmpRR_ogt(float %x, float %y) { 409; 410; CHECK-SF-LABEL: fcmpRR_ogt: 411; CHECK-SF: # %bb.0: # %entry 412; CHECK-SF-NEXT: fcmplts vr0, vr1 413; CHECK-SF-NEXT: mvc32 a0 414; CHECK-SF-NEXT: rts16 415; 416; CHECK-SF2-LABEL: fcmpRR_ogt: 417; CHECK-SF2: # %bb.0: # %entry 418; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1 419; CHECK-SF2-NEXT: mvc32 a0 420; CHECK-SF2-NEXT: rts16 421entry: 422 %fcmp = fcmp ogt float %y, %x 423 ret i1 %fcmp 424} 425 426define i1 @fcmpRI_ogt(float %x) { 427; 428; CHECK-SF-LABEL: fcmpRI_ogt: 429; CHECK-SF: # %bb.0: # %entry 430; CHECK-SF-NEXT: movih32 a0, 49440 431; CHECK-SF-NEXT: fmtvrl vr1, a0 432; CHECK-SF-NEXT: fcmplts vr1, vr0 433; CHECK-SF-NEXT: mvc32 a0 434; CHECK-SF-NEXT: rts16 435; 436; CHECK-SF2-LABEL: fcmpRI_ogt: 437; CHECK-SF2: # %bb.0: # %entry 438; CHECK-SF2-NEXT: movih32 a0, 49440 439; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 440; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0 441; CHECK-SF2-NEXT: mvc32 a0 442; CHECK-SF2-NEXT: rts16 443entry: 444 %fcmp = fcmp ogt float %x, -10.0 445 ret i1 %fcmp 446} 447 448define i1 @fcmpRI_X_ogt(float %x) { 449; 450; CHECK-SF-LABEL: fcmpRI_X_ogt: 451; CHECK-SF: # %bb.0: # %entry 452; CHECK-SF-NEXT: fcmpzlss vr0 453; CHECK-SF-NEXT: mvcv16 a0 454; CHECK-SF-NEXT: rts16 455; 456; CHECK-SF2-LABEL: fcmpRI_X_ogt: 457; CHECK-SF2: # %bb.0: # %entry 458; CHECK-SF2-NEXT: fcmphz.32 vr0 459; CHECK-SF2-NEXT: mvc32 a0 460; CHECK-SF2-NEXT: rts16 461entry: 462 %fcmp = fcmp ogt float %x, 0.0 463 ret i1 %fcmp 464} 465 466 467;oge 468define i1 @fcmpRR_oge(float %x, float %y) { 469; 470; CHECK-SF-LABEL: fcmpRR_oge: 471; CHECK-SF: # %bb.0: # %entry 472; CHECK-SF-NEXT: fcmphss vr1, vr0 473; CHECK-SF-NEXT: mvc32 a0 474; CHECK-SF-NEXT: rts16 475; 476; CHECK-SF2-LABEL: fcmpRR_oge: 477; CHECK-SF2: # %bb.0: # %entry 478; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0 479; CHECK-SF2-NEXT: mvc32 a0 480; CHECK-SF2-NEXT: rts16 481entry: 482 %fcmp = fcmp oge float %y, %x 483 ret i1 %fcmp 484} 485 486define i1 @fcmpRI_oge(float %x) { 487; 488; CHECK-SF-LABEL: fcmpRI_oge: 489; CHECK-SF: # %bb.0: # %entry 490; CHECK-SF-NEXT: movih32 a0, 49440 491; CHECK-SF-NEXT: fmtvrl vr1, a0 492; CHECK-SF-NEXT: fcmphss vr0, vr1 493; CHECK-SF-NEXT: mvc32 a0 494; CHECK-SF-NEXT: rts16 495; 496; CHECK-SF2-LABEL: fcmpRI_oge: 497; CHECK-SF2: # %bb.0: # %entry 498; CHECK-SF2-NEXT: movih32 a0, 49440 499; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 500; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1 501; CHECK-SF2-NEXT: mvc32 a0 502; CHECK-SF2-NEXT: rts16 503entry: 504 %fcmp = fcmp oge float %x, -10.0 505 ret i1 %fcmp 506} 507 508define i1 @fcmpRI_X_oge(float %x) { 509; 510; CHECK-SF-LABEL: fcmpRI_X_oge: 511; CHECK-SF: # %bb.0: # %entry 512; CHECK-SF-NEXT: fcmpzhss vr0 513; CHECK-SF-NEXT: mvc32 a0 514; CHECK-SF-NEXT: rts16 515; 516; CHECK-SF2-LABEL: fcmpRI_X_oge: 517; CHECK-SF2: # %bb.0: # %entry 518; CHECK-SF2-NEXT: fcmphsz.32 vr0 519; CHECK-SF2-NEXT: mvc32 a0 520; CHECK-SF2-NEXT: rts16 521entry: 522 %fcmp = fcmp oge float %x, 0.0 523 ret i1 %fcmp 524} 525 526 527;olt 528define i1 @fcmpRR_olt(float %x, float %y) { 529; 530; CHECK-SF-LABEL: fcmpRR_olt: 531; CHECK-SF: # %bb.0: # %entry 532; CHECK-SF-NEXT: fcmplts vr1, vr0 533; CHECK-SF-NEXT: mvc32 a0 534; CHECK-SF-NEXT: rts16 535; 536; CHECK-SF2-LABEL: fcmpRR_olt: 537; CHECK-SF2: # %bb.0: # %entry 538; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0 539; CHECK-SF2-NEXT: mvc32 a0 540; CHECK-SF2-NEXT: rts16 541entry: 542 %fcmp = fcmp olt float %y, %x 543 ret i1 %fcmp 544} 545 546define i1 @fcmpRI_olt(float %x) { 547; 548; CHECK-SF-LABEL: fcmpRI_olt: 549; CHECK-SF: # %bb.0: # %entry 550; CHECK-SF-NEXT: movih32 a0, 49440 551; CHECK-SF-NEXT: fmtvrl vr1, a0 552; CHECK-SF-NEXT: fcmplts vr0, vr1 553; CHECK-SF-NEXT: mvc32 a0 554; CHECK-SF-NEXT: rts16 555; 556; CHECK-SF2-LABEL: fcmpRI_olt: 557; CHECK-SF2: # %bb.0: # %entry 558; CHECK-SF2-NEXT: movih32 a0, 49440 559; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 560; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1 561; CHECK-SF2-NEXT: mvc32 a0 562; CHECK-SF2-NEXT: rts16 563entry: 564 %fcmp = fcmp olt float %x, -10.0 565 ret i1 %fcmp 566} 567 568define i1 @fcmpRI_X_olt(float %x) { 569; 570; CHECK-SF-LABEL: fcmpRI_X_olt: 571; CHECK-SF: # %bb.0: # %entry 572; CHECK-SF-NEXT: fcmpzhss vr0 573; CHECK-SF-NEXT: mvcv16 a0 574; CHECK-SF-NEXT: rts16 575; 576; CHECK-SF2-LABEL: fcmpRI_X_olt: 577; CHECK-SF2: # %bb.0: # %entry 578; CHECK-SF2-NEXT: fcmpltz.32 vr0 579; CHECK-SF2-NEXT: mvc32 a0 580; CHECK-SF2-NEXT: rts16 581entry: 582 %fcmp = fcmp olt float %x, 0.0 583 ret i1 %fcmp 584} 585 586 587;ole 588define i1 @fcmpRR_ole(float %x, float %y) { 589; 590; CHECK-SF-LABEL: fcmpRR_ole: 591; CHECK-SF: # %bb.0: # %entry 592; CHECK-SF-NEXT: fcmphss vr0, vr1 593; CHECK-SF-NEXT: mvc32 a0 594; CHECK-SF-NEXT: rts16 595; 596; CHECK-SF2-LABEL: fcmpRR_ole: 597; CHECK-SF2: # %bb.0: # %entry 598; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1 599; CHECK-SF2-NEXT: mvc32 a0 600; CHECK-SF2-NEXT: rts16 601entry: 602 %fcmp = fcmp ole float %y, %x 603 ret i1 %fcmp 604} 605 606define i1 @fcmpRI_ole(float %x) { 607; 608; CHECK-SF-LABEL: fcmpRI_ole: 609; CHECK-SF: # %bb.0: # %entry 610; CHECK-SF-NEXT: movih32 a0, 49440 611; CHECK-SF-NEXT: fmtvrl vr1, a0 612; CHECK-SF-NEXT: fcmphss vr1, vr0 613; CHECK-SF-NEXT: mvc32 a0 614; CHECK-SF-NEXT: rts16 615; 616; CHECK-SF2-LABEL: fcmpRI_ole: 617; CHECK-SF2: # %bb.0: # %entry 618; CHECK-SF2-NEXT: movih32 a0, 49440 619; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 620; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0 621; CHECK-SF2-NEXT: mvc32 a0 622; CHECK-SF2-NEXT: rts16 623entry: 624 %fcmp = fcmp ole float %x, -10.0 625 ret i1 %fcmp 626} 627 628define i1 @fcmpRI_X_ole(float %x) { 629; 630; CHECK-SF-LABEL: fcmpRI_X_ole: 631; CHECK-SF: # %bb.0: # %entry 632; CHECK-SF-NEXT: fcmpzlss vr0 633; CHECK-SF-NEXT: mvc32 a0 634; CHECK-SF-NEXT: rts16 635; 636; CHECK-SF2-LABEL: fcmpRI_X_ole: 637; CHECK-SF2: # %bb.0: # %entry 638; CHECK-SF2-NEXT: fcmplsz.32 vr0 639; CHECK-SF2-NEXT: mvc32 a0 640; CHECK-SF2-NEXT: rts16 641entry: 642 %fcmp = fcmp ole float %x, 0.0 643 ret i1 %fcmp 644} 645 646 647;one 648define i1 @fcmpRR_one(float %x, float %y) { 649; 650; CHECK-SF-LABEL: fcmpRR_one: 651; CHECK-SF: # %bb.0: # %entry 652; CHECK-SF-NEXT: fcmpuos vr1, vr0 653; CHECK-SF-NEXT: mvcv16 a0 654; CHECK-SF-NEXT: fcmpnes vr1, vr0 655; CHECK-SF-NEXT: mvc32 a1 656; CHECK-SF-NEXT: and16 a0, a1 657; CHECK-SF-NEXT: rts16 658; 659; CHECK-SF2-LABEL: fcmpRR_one: 660; CHECK-SF2: # %bb.0: # %entry 661; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0 662; CHECK-SF2-NEXT: mvcv16 a0 663; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0 664; CHECK-SF2-NEXT: mvc32 a1 665; CHECK-SF2-NEXT: and16 a0, a1 666; CHECK-SF2-NEXT: rts16 667entry: 668 %fcmp = fcmp one float %y, %x 669 ret i1 %fcmp 670} 671 672define i1 @fcmpRI_one(float %x) { 673; 674; CHECK-SF-LABEL: fcmpRI_one: 675; CHECK-SF: # %bb.0: # %entry 676; CHECK-SF-NEXT: movih32 a0, 49440 677; CHECK-SF-NEXT: fmtvrl vr1, a0 678; CHECK-SF-NEXT: fcmpnes vr0, vr1 679; CHECK-SF-NEXT: mvc32 a0 680; CHECK-SF-NEXT: fcmpuos vr0, vr0 681; CHECK-SF-NEXT: mvcv16 a1 682; CHECK-SF-NEXT: and16 a0, a1 683; CHECK-SF-NEXT: rts16 684; 685; CHECK-SF2-LABEL: fcmpRI_one: 686; CHECK-SF2: # %bb.0: # %entry 687; CHECK-SF2-NEXT: movih32 a0, 49440 688; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 689; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1 690; CHECK-SF2-NEXT: mvc32 a0 691; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0 692; CHECK-SF2-NEXT: mvcv16 a1 693; CHECK-SF2-NEXT: and16 a0, a1 694; CHECK-SF2-NEXT: rts16 695entry: 696 %fcmp = fcmp one float %x, -10.0 697 ret i1 %fcmp 698} 699 700define i1 @fcmpRI_X_one(float %x) { 701; 702; CHECK-SF-LABEL: fcmpRI_X_one: 703; CHECK-SF: # %bb.0: # %entry 704; CHECK-SF-NEXT: fcmpuos vr0, vr0 705; CHECK-SF-NEXT: mvcv16 a0 706; CHECK-SF-NEXT: fcmpznes vr0 707; CHECK-SF-NEXT: mvc32 a1 708; CHECK-SF-NEXT: and16 a0, a1 709; CHECK-SF-NEXT: rts16 710; 711; CHECK-SF2-LABEL: fcmpRI_X_one: 712; CHECK-SF2: # %bb.0: # %entry 713; CHECK-SF2-NEXT: movi16 a0, 0 714; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 715; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1 716; CHECK-SF2-NEXT: mvc32 a0 717; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0 718; CHECK-SF2-NEXT: mvcv16 a1 719; CHECK-SF2-NEXT: and16 a0, a1 720; CHECK-SF2-NEXT: rts16 721entry: 722 %fcmp = fcmp one float %x, 0.0 723 ret i1 %fcmp 724} 725 726 727;oeq 728define i1 @fcmpRR_oeq(float %x, float %y) { 729; 730; CHECK-SF-LABEL: fcmpRR_oeq: 731; CHECK-SF: # %bb.0: # %entry 732; CHECK-SF-NEXT: fcmpnes vr1, vr0 733; CHECK-SF-NEXT: mvcv16 a0 734; CHECK-SF-NEXT: rts16 735; 736; CHECK-SF2-LABEL: fcmpRR_oeq: 737; CHECK-SF2: # %bb.0: # %entry 738; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0 739; CHECK-SF2-NEXT: mvcv16 a0 740; CHECK-SF2-NEXT: rts16 741entry: 742 %fcmp = fcmp oeq float %y, %x 743 ret i1 %fcmp 744} 745 746define i1 @fcmpRI_oeq(float %x) { 747; 748; CHECK-SF-LABEL: fcmpRI_oeq: 749; CHECK-SF: # %bb.0: # %entry 750; CHECK-SF-NEXT: movih32 a0, 49440 751; CHECK-SF-NEXT: fmtvrl vr1, a0 752; CHECK-SF-NEXT: fcmpnes vr0, vr1 753; CHECK-SF-NEXT: mvcv16 a0 754; CHECK-SF-NEXT: rts16 755; 756; CHECK-SF2-LABEL: fcmpRI_oeq: 757; CHECK-SF2: # %bb.0: # %entry 758; CHECK-SF2-NEXT: movih32 a0, 49440 759; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0 760; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1 761; CHECK-SF2-NEXT: mvcv16 a0 762; CHECK-SF2-NEXT: rts16 763entry: 764 %fcmp = fcmp oeq float %x, -10.0 765 ret i1 %fcmp 766} 767 768define i1 @fcmpRI_X_oeq(float %x) { 769; 770; CHECK-SF-LABEL: fcmpRI_X_oeq: 771; CHECK-SF: # %bb.0: # %entry 772; CHECK-SF-NEXT: fcmpznes vr0 773; CHECK-SF-NEXT: mvcv16 a0 774; CHECK-SF-NEXT: rts16 775; 776; CHECK-SF2-LABEL: fcmpRI_X_oeq: 777; CHECK-SF2: # %bb.0: # %entry 778; CHECK-SF2-NEXT: fcmpnez.32 vr0 779; CHECK-SF2-NEXT: mvcv16 a0 780; CHECK-SF2-NEXT: rts16 781entry: 782 %fcmp = fcmp oeq float %x, 0.0 783 ret i1 %fcmp 784} 785 786 787;ord 788define i1 @fcmpRR_ord(float %x, float %y) { 789; 790; CHECK-SF-LABEL: fcmpRR_ord: 791; CHECK-SF: # %bb.0: # %entry 792; CHECK-SF-NEXT: fcmpuos vr1, vr0 793; CHECK-SF-NEXT: mvcv16 a0 794; CHECK-SF-NEXT: rts16 795; 796; CHECK-SF2-LABEL: fcmpRR_ord: 797; CHECK-SF2: # %bb.0: # %entry 798; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0 799; CHECK-SF2-NEXT: mvcv16 a0 800; CHECK-SF2-NEXT: rts16 801entry: 802 %fcmp = fcmp ord float %y, %x 803 ret i1 %fcmp 804} 805 806define i1 @fcmpRI_ord(float %x) { 807; 808; CHECK-SF-LABEL: fcmpRI_ord: 809; CHECK-SF: # %bb.0: # %entry 810; CHECK-SF-NEXT: fcmpuos vr0, vr0 811; CHECK-SF-NEXT: mvcv16 a0 812; CHECK-SF-NEXT: rts16 813; 814; CHECK-SF2-LABEL: fcmpRI_ord: 815; CHECK-SF2: # %bb.0: # %entry 816; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0 817; CHECK-SF2-NEXT: mvcv16 a0 818; CHECK-SF2-NEXT: rts16 819entry: 820 %fcmp = fcmp ord float %x, -10.0 821 ret i1 %fcmp 822} 823 824define i1 @fcmpRI_X_ord(float %x) { 825; 826; CHECK-SF-LABEL: fcmpRI_X_ord: 827; CHECK-SF: # %bb.0: # %entry 828; CHECK-SF-NEXT: fcmpuos vr0, vr0 829; CHECK-SF-NEXT: mvcv16 a0 830; CHECK-SF-NEXT: rts16 831; 832; CHECK-SF2-LABEL: fcmpRI_X_ord: 833; CHECK-SF2: # %bb.0: # %entry 834; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0 835; CHECK-SF2-NEXT: mvcv16 a0 836; CHECK-SF2-NEXT: rts16 837entry: 838 %fcmp = fcmp ord float %x, 0.0 839 ret i1 %fcmp 840} 841 842 843;uno 844define i1 @fcmpRR_uno(float %x, float %y) { 845; 846; CHECK-SF-LABEL: fcmpRR_uno: 847; CHECK-SF: # %bb.0: # %entry 848; CHECK-SF-NEXT: fcmpuos vr1, vr0 849; CHECK-SF-NEXT: mvc32 a0 850; CHECK-SF-NEXT: rts16 851; 852; CHECK-SF2-LABEL: fcmpRR_uno: 853; CHECK-SF2: # %bb.0: # %entry 854; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0 855; CHECK-SF2-NEXT: mvc32 a0 856; CHECK-SF2-NEXT: rts16 857entry: 858 %fcmp = fcmp uno float %y, %x 859 ret i1 %fcmp 860} 861 862define i1 @fcmpRI_uno(float %x) { 863; 864; CHECK-SF-LABEL: fcmpRI_uno: 865; CHECK-SF: # %bb.0: # %entry 866; CHECK-SF-NEXT: fcmpuos vr0, vr0 867; CHECK-SF-NEXT: mvc32 a0 868; CHECK-SF-NEXT: rts16 869; 870; CHECK-SF2-LABEL: fcmpRI_uno: 871; CHECK-SF2: # %bb.0: # %entry 872; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0 873; CHECK-SF2-NEXT: mvc32 a0 874; CHECK-SF2-NEXT: rts16 875entry: 876 %fcmp = fcmp uno float %x, -10.0 877 ret i1 %fcmp 878} 879 880define i1 @fcmpRI_X_uno(float %x) { 881; 882; CHECK-SF-LABEL: fcmpRI_X_uno: 883; CHECK-SF: # %bb.0: # %entry 884; CHECK-SF-NEXT: fcmpuos vr0, vr0 885; CHECK-SF-NEXT: mvc32 a0 886; CHECK-SF-NEXT: rts16 887; 888; CHECK-SF2-LABEL: fcmpRI_X_uno: 889; CHECK-SF2: # %bb.0: # %entry 890; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0 891; CHECK-SF2-NEXT: mvc32 a0 892; CHECK-SF2-NEXT: rts16 893entry: 894 %fcmp = fcmp uno float %x, 0.0 895 ret i1 %fcmp 896} 897