1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 3; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF 4; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2 5 6 7;ueq 8 9define i1 @FCMP_DOUBLE_ueq(double %x, double %y) { 10; 11; 12; CHECK-DF-LABEL: FCMP_DOUBLE_ueq: 13; CHECK-DF: # %bb.0: # %entry 14; CHECK-DF-NEXT: fcmpuod vr1, vr0 15; CHECK-DF-NEXT: mvc32 a0 16; CHECK-DF-NEXT: fcmpned vr1, vr0 17; CHECK-DF-NEXT: mvcv16 a1 18; CHECK-DF-NEXT: or16 a0, a1 19; CHECK-DF-NEXT: rts16 20; 21; CHECK-DF2-LABEL: FCMP_DOUBLE_ueq: 22; CHECK-DF2: # %bb.0: # %entry 23; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0 24; CHECK-DF2-NEXT: mvc32 a0 25; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0 26; CHECK-DF2-NEXT: mvcv16 a1 27; CHECK-DF2-NEXT: or16 a0, a1 28; CHECK-DF2-NEXT: rts16 29entry: 30 %fcmp = fcmp ueq double %y, %x 31 ret i1 %fcmp 32} 33 34define i1 @FCMP_DOUBLE_I_ueq(double %x) { 35; 36; 37; CHECK-DF-LABEL: FCMP_DOUBLE_I_ueq: 38; CHECK-DF: # %bb.0: # %entry 39; CHECK-DF-NEXT: grs32 a0, .LCPI1_0 40; CHECK-DF-NEXT: fldd vr1, (a0, 0) 41; CHECK-DF-NEXT: fcmpuod vr0, vr1 42; CHECK-DF-NEXT: mvc32 a0 43; CHECK-DF-NEXT: fcmpned vr0, vr1 44; CHECK-DF-NEXT: mvcv16 a1 45; CHECK-DF-NEXT: or16 a0, a1 46; CHECK-DF-NEXT: rts16 47; CHECK-DF-NEXT: .p2align 1 48; CHECK-DF-NEXT: # %bb.1: 49; CHECK-DF-NEXT: .p2align 2 50; CHECK-DF-NEXT: .LCPI1_0: 51; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 52; 53; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ueq: 54; CHECK-DF2: # %bb.0: # %entry 55; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI1_0] 56; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr1 57; CHECK-DF2-NEXT: mvc32 a0 58; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1 59; CHECK-DF2-NEXT: mvcv16 a1 60; CHECK-DF2-NEXT: or16 a0, a1 61; CHECK-DF2-NEXT: rts16 62; CHECK-DF2-NEXT: .p2align 1 63; CHECK-DF2-NEXT: # %bb.1: 64; CHECK-DF2-NEXT: .p2align 2 65; CHECK-DF2-NEXT: .LCPI1_0: 66; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 67entry: 68 %fcmp = fcmp ueq double %x, 0.0 69 ret i1 %fcmp 70} 71 72;une 73 74define i1 @FCMP_DOUBLE_une(double %x, double %y) { 75; 76; 77; CHECK-DF-LABEL: FCMP_DOUBLE_une: 78; CHECK-DF: # %bb.0: # %entry 79; CHECK-DF-NEXT: fcmpned vr1, vr0 80; CHECK-DF-NEXT: mvc32 a0 81; CHECK-DF-NEXT: rts16 82; 83; CHECK-DF2-LABEL: FCMP_DOUBLE_une: 84; CHECK-DF2: # %bb.0: # %entry 85; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0 86; CHECK-DF2-NEXT: mvc32 a0 87; CHECK-DF2-NEXT: rts16 88entry: 89 %fcmp = fcmp une double %y, %x 90 ret i1 %fcmp 91} 92 93define i1 @FCMP_DOUBLE_I_une(double %x) { 94; 95; 96; CHECK-DF-LABEL: FCMP_DOUBLE_I_une: 97; CHECK-DF: # %bb.0: # %entry 98; CHECK-DF-NEXT: grs32 a0, .LCPI3_0 99; CHECK-DF-NEXT: fldd vr1, (a0, 0) 100; CHECK-DF-NEXT: fcmpned vr0, vr1 101; CHECK-DF-NEXT: mvc32 a0 102; CHECK-DF-NEXT: rts16 103; CHECK-DF-NEXT: .p2align 1 104; CHECK-DF-NEXT: # %bb.1: 105; CHECK-DF-NEXT: .p2align 2 106; CHECK-DF-NEXT: .LCPI3_0: 107; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 108; 109; CHECK-DF2-LABEL: FCMP_DOUBLE_I_une: 110; CHECK-DF2: # %bb.0: # %entry 111; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI3_0] 112; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1 113; CHECK-DF2-NEXT: mvc32 a0 114; CHECK-DF2-NEXT: rts16 115; CHECK-DF2-NEXT: .p2align 1 116; CHECK-DF2-NEXT: # %bb.1: 117; CHECK-DF2-NEXT: .p2align 2 118; CHECK-DF2-NEXT: .LCPI3_0: 119; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 120entry: 121 %fcmp = fcmp une double %x, 0.0 122 ret i1 %fcmp 123} 124 125;ugt 126 127define i1 @FCMP_DOUBLE_ugt(double %x, double %y) { 128; 129; 130; CHECK-DF-LABEL: FCMP_DOUBLE_ugt: 131; CHECK-DF: # %bb.0: # %entry 132; CHECK-DF-NEXT: fcmphsd vr0, vr1 133; CHECK-DF-NEXT: mvc32 a0 134; CHECK-DF-NEXT: xori32 a0, a0, 1 135; CHECK-DF-NEXT: rts16 136; 137; CHECK-DF2-LABEL: FCMP_DOUBLE_ugt: 138; CHECK-DF2: # %bb.0: # %entry 139; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1 140; CHECK-DF2-NEXT: mvc32 a0 141; CHECK-DF2-NEXT: xori32 a0, a0, 1 142; CHECK-DF2-NEXT: rts16 143entry: 144 %fcmp = fcmp ugt double %y, %x 145 ret i1 %fcmp 146} 147 148define i1 @FCMP_DOUBLE_I_ugt(double %x) { 149; 150; 151; CHECK-DF-LABEL: FCMP_DOUBLE_I_ugt: 152; CHECK-DF: # %bb.0: # %entry 153; CHECK-DF-NEXT: grs32 a0, .LCPI5_0 154; CHECK-DF-NEXT: fldd vr1, (a0, 0) 155; CHECK-DF-NEXT: fcmphsd vr1, vr0 156; CHECK-DF-NEXT: mvc32 a0 157; CHECK-DF-NEXT: xori32 a0, a0, 1 158; CHECK-DF-NEXT: rts16 159; CHECK-DF-NEXT: .p2align 1 160; CHECK-DF-NEXT: # %bb.1: 161; CHECK-DF-NEXT: .p2align 2 162; CHECK-DF-NEXT: .LCPI5_0: 163; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 164; 165; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ugt: 166; CHECK-DF2: # %bb.0: # %entry 167; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI5_0] 168; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0 169; CHECK-DF2-NEXT: mvc32 a0 170; CHECK-DF2-NEXT: xori32 a0, a0, 1 171; CHECK-DF2-NEXT: rts16 172; CHECK-DF2-NEXT: .p2align 1 173; CHECK-DF2-NEXT: # %bb.1: 174; CHECK-DF2-NEXT: .p2align 2 175; CHECK-DF2-NEXT: .LCPI5_0: 176; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 177entry: 178 %fcmp = fcmp ugt double %x, 0.0 179 ret i1 %fcmp 180} 181 182 183;uge 184 185define i1 @FCMP_DOUBLE_uge(double %x, double %y) { 186; 187; 188; CHECK-DF-LABEL: FCMP_DOUBLE_uge: 189; CHECK-DF: # %bb.0: # %entry 190; CHECK-DF-NEXT: fcmpltd vr1, vr0 191; CHECK-DF-NEXT: mvc32 a0 192; CHECK-DF-NEXT: xori32 a0, a0, 1 193; CHECK-DF-NEXT: rts16 194; 195; CHECK-DF2-LABEL: FCMP_DOUBLE_uge: 196; CHECK-DF2: # %bb.0: # %entry 197; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0 198; CHECK-DF2-NEXT: mvc32 a0 199; CHECK-DF2-NEXT: xori32 a0, a0, 1 200; CHECK-DF2-NEXT: rts16 201entry: 202 %fcmp = fcmp uge double %y, %x 203 ret i1 %fcmp 204} 205 206define i1 @FCMP_DOUBLE_I_uge(double %x) { 207; 208; 209; CHECK-DF-LABEL: FCMP_DOUBLE_I_uge: 210; CHECK-DF: # %bb.0: # %entry 211; CHECK-DF-NEXT: grs32 a0, .LCPI7_0 212; CHECK-DF-NEXT: fldd vr1, (a0, 0) 213; CHECK-DF-NEXT: fcmpltd vr0, vr1 214; CHECK-DF-NEXT: mvc32 a0 215; CHECK-DF-NEXT: xori32 a0, a0, 1 216; CHECK-DF-NEXT: rts16 217; CHECK-DF-NEXT: .p2align 1 218; CHECK-DF-NEXT: # %bb.1: 219; CHECK-DF-NEXT: .p2align 2 220; CHECK-DF-NEXT: .LCPI7_0: 221; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 222; 223; CHECK-DF2-LABEL: FCMP_DOUBLE_I_uge: 224; CHECK-DF2: # %bb.0: # %entry 225; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI7_0] 226; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1 227; CHECK-DF2-NEXT: mvc32 a0 228; CHECK-DF2-NEXT: xori32 a0, a0, 1 229; CHECK-DF2-NEXT: rts16 230; CHECK-DF2-NEXT: .p2align 1 231; CHECK-DF2-NEXT: # %bb.1: 232; CHECK-DF2-NEXT: .p2align 2 233; CHECK-DF2-NEXT: .LCPI7_0: 234; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 235entry: 236 %fcmp = fcmp uge double %x, 0.0 237 ret i1 %fcmp 238} 239 240 241;ult 242 243define i1 @FCMP_DOUBLE_ult(double %x, double %y) { 244; 245; 246; CHECK-DF-LABEL: FCMP_DOUBLE_ult: 247; CHECK-DF: # %bb.0: # %entry 248; CHECK-DF-NEXT: fcmphsd vr1, vr0 249; CHECK-DF-NEXT: mvc32 a0 250; CHECK-DF-NEXT: xori32 a0, a0, 1 251; CHECK-DF-NEXT: rts16 252; 253; CHECK-DF2-LABEL: FCMP_DOUBLE_ult: 254; CHECK-DF2: # %bb.0: # %entry 255; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0 256; CHECK-DF2-NEXT: mvc32 a0 257; CHECK-DF2-NEXT: xori32 a0, a0, 1 258; CHECK-DF2-NEXT: rts16 259entry: 260 %fcmp = fcmp ult double %y, %x 261 ret i1 %fcmp 262} 263 264define i1 @FCMP_DOUBLE_I_ult(double %x) { 265; 266; 267; CHECK-DF-LABEL: FCMP_DOUBLE_I_ult: 268; CHECK-DF: # %bb.0: # %entry 269; CHECK-DF-NEXT: grs32 a0, .LCPI9_0 270; CHECK-DF-NEXT: fldd vr1, (a0, 0) 271; CHECK-DF-NEXT: fcmphsd vr0, vr1 272; CHECK-DF-NEXT: mvc32 a0 273; CHECK-DF-NEXT: xori32 a0, a0, 1 274; CHECK-DF-NEXT: rts16 275; CHECK-DF-NEXT: .p2align 1 276; CHECK-DF-NEXT: # %bb.1: 277; CHECK-DF-NEXT: .p2align 2 278; CHECK-DF-NEXT: .LCPI9_0: 279; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 280; 281; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ult: 282; CHECK-DF2: # %bb.0: # %entry 283; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI9_0] 284; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1 285; CHECK-DF2-NEXT: mvc32 a0 286; CHECK-DF2-NEXT: xori32 a0, a0, 1 287; CHECK-DF2-NEXT: rts16 288; CHECK-DF2-NEXT: .p2align 1 289; CHECK-DF2-NEXT: # %bb.1: 290; CHECK-DF2-NEXT: .p2align 2 291; CHECK-DF2-NEXT: .LCPI9_0: 292; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 293entry: 294 %fcmp = fcmp ult double %x, 0.0 295 ret i1 %fcmp 296} 297 298 299;ule 300 301define i1 @FCMP_DOUBLE_ule(double %x, double %y) { 302; 303; 304; CHECK-DF-LABEL: FCMP_DOUBLE_ule: 305; CHECK-DF: # %bb.0: # %entry 306; CHECK-DF-NEXT: fcmpltd vr0, vr1 307; CHECK-DF-NEXT: mvc32 a0 308; CHECK-DF-NEXT: xori32 a0, a0, 1 309; CHECK-DF-NEXT: rts16 310; 311; CHECK-DF2-LABEL: FCMP_DOUBLE_ule: 312; CHECK-DF2: # %bb.0: # %entry 313; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1 314; CHECK-DF2-NEXT: mvc32 a0 315; CHECK-DF2-NEXT: xori32 a0, a0, 1 316; CHECK-DF2-NEXT: rts16 317entry: 318 %fcmp = fcmp ule double %y, %x 319 ret i1 %fcmp 320} 321 322define i1 @FCMP_DOUBLE_I_ule(double %x) { 323; 324; 325; CHECK-DF-LABEL: FCMP_DOUBLE_I_ule: 326; CHECK-DF: # %bb.0: # %entry 327; CHECK-DF-NEXT: grs32 a0, .LCPI11_0 328; CHECK-DF-NEXT: fldd vr1, (a0, 0) 329; CHECK-DF-NEXT: fcmpltd vr1, vr0 330; CHECK-DF-NEXT: mvc32 a0 331; CHECK-DF-NEXT: xori32 a0, a0, 1 332; CHECK-DF-NEXT: rts16 333; CHECK-DF-NEXT: .p2align 1 334; CHECK-DF-NEXT: # %bb.1: 335; CHECK-DF-NEXT: .p2align 2 336; CHECK-DF-NEXT: .LCPI11_0: 337; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 338; 339; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ule: 340; CHECK-DF2: # %bb.0: # %entry 341; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI11_0] 342; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0 343; CHECK-DF2-NEXT: mvc32 a0 344; CHECK-DF2-NEXT: xori32 a0, a0, 1 345; CHECK-DF2-NEXT: rts16 346; CHECK-DF2-NEXT: .p2align 1 347; CHECK-DF2-NEXT: # %bb.1: 348; CHECK-DF2-NEXT: .p2align 2 349; CHECK-DF2-NEXT: .LCPI11_0: 350; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 351entry: 352 %fcmp = fcmp ule double %x, 0.0 353 ret i1 %fcmp 354} 355 356 357;ogt 358 359define i1 @FCMP_DOUBLE_ogt(double %x, double %y) { 360; 361; 362; CHECK-DF-LABEL: FCMP_DOUBLE_ogt: 363; CHECK-DF: # %bb.0: # %entry 364; CHECK-DF-NEXT: fcmpltd vr0, vr1 365; CHECK-DF-NEXT: mvc32 a0 366; CHECK-DF-NEXT: rts16 367; 368; CHECK-DF2-LABEL: FCMP_DOUBLE_ogt: 369; CHECK-DF2: # %bb.0: # %entry 370; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1 371; CHECK-DF2-NEXT: mvc32 a0 372; CHECK-DF2-NEXT: rts16 373entry: 374 %fcmp = fcmp ogt double %y, %x 375 ret i1 %fcmp 376} 377 378define i1 @FCMP_DOUBLE_I_ogt(double %x) { 379; 380; 381; CHECK-DF-LABEL: FCMP_DOUBLE_I_ogt: 382; CHECK-DF: # %bb.0: # %entry 383; CHECK-DF-NEXT: grs32 a0, .LCPI13_0 384; CHECK-DF-NEXT: fldd vr1, (a0, 0) 385; CHECK-DF-NEXT: fcmpltd vr1, vr0 386; CHECK-DF-NEXT: mvc32 a0 387; CHECK-DF-NEXT: rts16 388; CHECK-DF-NEXT: .p2align 1 389; CHECK-DF-NEXT: # %bb.1: 390; CHECK-DF-NEXT: .p2align 2 391; CHECK-DF-NEXT: .LCPI13_0: 392; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 393; 394; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ogt: 395; CHECK-DF2: # %bb.0: # %entry 396; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI13_0] 397; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0 398; CHECK-DF2-NEXT: mvc32 a0 399; CHECK-DF2-NEXT: rts16 400; CHECK-DF2-NEXT: .p2align 1 401; CHECK-DF2-NEXT: # %bb.1: 402; CHECK-DF2-NEXT: .p2align 2 403; CHECK-DF2-NEXT: .LCPI13_0: 404; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 405entry: 406 %fcmp = fcmp ogt double %x, 0.0 407 ret i1 %fcmp 408} 409 410;oge 411 412define i1 @FCMP_DOUBLE_oge(double %x, double %y) { 413; 414; 415; CHECK-DF-LABEL: FCMP_DOUBLE_oge: 416; CHECK-DF: # %bb.0: # %entry 417; CHECK-DF-NEXT: fcmphsd vr1, vr0 418; CHECK-DF-NEXT: mvc32 a0 419; CHECK-DF-NEXT: rts16 420; 421; CHECK-DF2-LABEL: FCMP_DOUBLE_oge: 422; CHECK-DF2: # %bb.0: # %entry 423; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0 424; CHECK-DF2-NEXT: mvc32 a0 425; CHECK-DF2-NEXT: rts16 426entry: 427 %fcmp = fcmp oge double %y, %x 428 ret i1 %fcmp 429} 430 431define i1 @FCMP_DOUBLE_I_oge(double %x) { 432; 433; 434; CHECK-DF-LABEL: FCMP_DOUBLE_I_oge: 435; CHECK-DF: # %bb.0: # %entry 436; CHECK-DF-NEXT: grs32 a0, .LCPI15_0 437; CHECK-DF-NEXT: fldd vr1, (a0, 0) 438; CHECK-DF-NEXT: fcmphsd vr0, vr1 439; CHECK-DF-NEXT: mvc32 a0 440; CHECK-DF-NEXT: rts16 441; CHECK-DF-NEXT: .p2align 1 442; CHECK-DF-NEXT: # %bb.1: 443; CHECK-DF-NEXT: .p2align 2 444; CHECK-DF-NEXT: .LCPI15_0: 445; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 446; 447; CHECK-DF2-LABEL: FCMP_DOUBLE_I_oge: 448; CHECK-DF2: # %bb.0: # %entry 449; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI15_0] 450; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1 451; CHECK-DF2-NEXT: mvc32 a0 452; CHECK-DF2-NEXT: rts16 453; CHECK-DF2-NEXT: .p2align 1 454; CHECK-DF2-NEXT: # %bb.1: 455; CHECK-DF2-NEXT: .p2align 2 456; CHECK-DF2-NEXT: .LCPI15_0: 457; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 458entry: 459 %fcmp = fcmp oge double %x, 0.0 460 ret i1 %fcmp 461} 462 463 464;olt 465 466define i1 @FCMP_DOUBLE_olt(double %x, double %y) { 467; 468; 469; CHECK-DF-LABEL: FCMP_DOUBLE_olt: 470; CHECK-DF: # %bb.0: # %entry 471; CHECK-DF-NEXT: fcmpltd vr1, vr0 472; CHECK-DF-NEXT: mvc32 a0 473; CHECK-DF-NEXT: rts16 474; 475; CHECK-DF2-LABEL: FCMP_DOUBLE_olt: 476; CHECK-DF2: # %bb.0: # %entry 477; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0 478; CHECK-DF2-NEXT: mvc32 a0 479; CHECK-DF2-NEXT: rts16 480entry: 481 %fcmp = fcmp olt double %y, %x 482 ret i1 %fcmp 483} 484 485define i1 @FCMP_DOUBLE_I_olt(double %x) { 486; 487; 488; CHECK-DF-LABEL: FCMP_DOUBLE_I_olt: 489; CHECK-DF: # %bb.0: # %entry 490; CHECK-DF-NEXT: grs32 a0, .LCPI17_0 491; CHECK-DF-NEXT: fldd vr1, (a0, 0) 492; CHECK-DF-NEXT: fcmpltd vr0, vr1 493; CHECK-DF-NEXT: mvc32 a0 494; CHECK-DF-NEXT: rts16 495; CHECK-DF-NEXT: .p2align 1 496; CHECK-DF-NEXT: # %bb.1: 497; CHECK-DF-NEXT: .p2align 2 498; CHECK-DF-NEXT: .LCPI17_0: 499; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 500; 501; CHECK-DF2-LABEL: FCMP_DOUBLE_I_olt: 502; CHECK-DF2: # %bb.0: # %entry 503; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI17_0] 504; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1 505; CHECK-DF2-NEXT: mvc32 a0 506; CHECK-DF2-NEXT: rts16 507; CHECK-DF2-NEXT: .p2align 1 508; CHECK-DF2-NEXT: # %bb.1: 509; CHECK-DF2-NEXT: .p2align 2 510; CHECK-DF2-NEXT: .LCPI17_0: 511; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 512entry: 513 %fcmp = fcmp olt double %x, 0.0 514 ret i1 %fcmp 515} 516 517;ole 518 519define i1 @FCMP_DOUBLE_ole(double %x, double %y) { 520; 521; 522; CHECK-DF-LABEL: FCMP_DOUBLE_ole: 523; CHECK-DF: # %bb.0: # %entry 524; CHECK-DF-NEXT: fcmphsd vr0, vr1 525; CHECK-DF-NEXT: mvc32 a0 526; CHECK-DF-NEXT: rts16 527; 528; CHECK-DF2-LABEL: FCMP_DOUBLE_ole: 529; CHECK-DF2: # %bb.0: # %entry 530; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1 531; CHECK-DF2-NEXT: mvc32 a0 532; CHECK-DF2-NEXT: rts16 533entry: 534 %fcmp = fcmp ole double %y, %x 535 ret i1 %fcmp 536} 537 538define i1 @FCMP_DOUBLE_I_ole(double %x) { 539; 540; 541; CHECK-DF-LABEL: FCMP_DOUBLE_I_ole: 542; CHECK-DF: # %bb.0: # %entry 543; CHECK-DF-NEXT: grs32 a0, .LCPI19_0 544; CHECK-DF-NEXT: fldd vr1, (a0, 0) 545; CHECK-DF-NEXT: fcmphsd vr1, vr0 546; CHECK-DF-NEXT: mvc32 a0 547; CHECK-DF-NEXT: rts16 548; CHECK-DF-NEXT: .p2align 1 549; CHECK-DF-NEXT: # %bb.1: 550; CHECK-DF-NEXT: .p2align 2 551; CHECK-DF-NEXT: .LCPI19_0: 552; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 553; 554; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ole: 555; CHECK-DF2: # %bb.0: # %entry 556; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI19_0] 557; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0 558; CHECK-DF2-NEXT: mvc32 a0 559; CHECK-DF2-NEXT: rts16 560; CHECK-DF2-NEXT: .p2align 1 561; CHECK-DF2-NEXT: # %bb.1: 562; CHECK-DF2-NEXT: .p2align 2 563; CHECK-DF2-NEXT: .LCPI19_0: 564; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 565entry: 566 %fcmp = fcmp ole double %x, 0.0 567 ret i1 %fcmp 568} 569 570;one 571 572define i1 @FCMP_DOUBLE_one(double %x, double %y) { 573; 574; 575; CHECK-DF-LABEL: FCMP_DOUBLE_one: 576; CHECK-DF: # %bb.0: # %entry 577; CHECK-DF-NEXT: fcmpuod vr1, vr0 578; CHECK-DF-NEXT: mvcv16 a0 579; CHECK-DF-NEXT: fcmpned vr1, vr0 580; CHECK-DF-NEXT: mvc32 a1 581; CHECK-DF-NEXT: and16 a0, a1 582; CHECK-DF-NEXT: rts16 583; 584; CHECK-DF2-LABEL: FCMP_DOUBLE_one: 585; CHECK-DF2: # %bb.0: # %entry 586; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0 587; CHECK-DF2-NEXT: mvcv16 a0 588; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0 589; CHECK-DF2-NEXT: mvc32 a1 590; CHECK-DF2-NEXT: and16 a0, a1 591; CHECK-DF2-NEXT: rts16 592entry: 593 %fcmp = fcmp one double %y, %x 594 ret i1 %fcmp 595} 596 597define i1 @FCMP_DOUBLE_I_one(double %x) { 598; 599; 600; CHECK-DF-LABEL: FCMP_DOUBLE_I_one: 601; CHECK-DF: # %bb.0: # %entry 602; CHECK-DF-NEXT: grs32 a0, .LCPI21_0 603; CHECK-DF-NEXT: fldd vr1, (a0, 0) 604; CHECK-DF-NEXT: fcmpuod vr0, vr1 605; CHECK-DF-NEXT: mvcv16 a0 606; CHECK-DF-NEXT: fcmpned vr0, vr1 607; CHECK-DF-NEXT: mvc32 a1 608; CHECK-DF-NEXT: and16 a0, a1 609; CHECK-DF-NEXT: rts16 610; CHECK-DF-NEXT: .p2align 1 611; CHECK-DF-NEXT: # %bb.1: 612; CHECK-DF-NEXT: .p2align 2 613; CHECK-DF-NEXT: .LCPI21_0: 614; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 615; 616; CHECK-DF2-LABEL: FCMP_DOUBLE_I_one: 617; CHECK-DF2: # %bb.0: # %entry 618; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI21_0] 619; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr1 620; CHECK-DF2-NEXT: mvcv16 a0 621; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1 622; CHECK-DF2-NEXT: mvc32 a1 623; CHECK-DF2-NEXT: and16 a0, a1 624; CHECK-DF2-NEXT: rts16 625; CHECK-DF2-NEXT: .p2align 1 626; CHECK-DF2-NEXT: # %bb.1: 627; CHECK-DF2-NEXT: .p2align 2 628; CHECK-DF2-NEXT: .LCPI21_0: 629; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 630entry: 631 %fcmp = fcmp one double %x, 0.0 632 ret i1 %fcmp 633} 634 635;oeq 636 637define i1 @FCMP_DOUBLE_oeq(double %x, double %y) { 638; 639; 640; CHECK-DF-LABEL: FCMP_DOUBLE_oeq: 641; CHECK-DF: # %bb.0: # %entry 642; CHECK-DF-NEXT: fcmpned vr1, vr0 643; CHECK-DF-NEXT: mvcv16 a0 644; CHECK-DF-NEXT: rts16 645; 646; CHECK-DF2-LABEL: FCMP_DOUBLE_oeq: 647; CHECK-DF2: # %bb.0: # %entry 648; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0 649; CHECK-DF2-NEXT: mvcv16 a0 650; CHECK-DF2-NEXT: rts16 651entry: 652 %fcmp = fcmp oeq double %y, %x 653 ret i1 %fcmp 654} 655 656define i1 @FCMP_DOUBLE_I_oeq(double %x) { 657; 658; 659; CHECK-DF-LABEL: FCMP_DOUBLE_I_oeq: 660; CHECK-DF: # %bb.0: # %entry 661; CHECK-DF-NEXT: grs32 a0, .LCPI23_0 662; CHECK-DF-NEXT: fldd vr1, (a0, 0) 663; CHECK-DF-NEXT: fcmpned vr0, vr1 664; CHECK-DF-NEXT: mvcv16 a0 665; CHECK-DF-NEXT: rts16 666; CHECK-DF-NEXT: .p2align 1 667; CHECK-DF-NEXT: # %bb.1: 668; CHECK-DF-NEXT: .p2align 2 669; CHECK-DF-NEXT: .LCPI23_0: 670; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0 671; 672; CHECK-DF2-LABEL: FCMP_DOUBLE_I_oeq: 673; CHECK-DF2: # %bb.0: # %entry 674; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI23_0] 675; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1 676; CHECK-DF2-NEXT: mvcv16 a0 677; CHECK-DF2-NEXT: rts16 678; CHECK-DF2-NEXT: .p2align 1 679; CHECK-DF2-NEXT: # %bb.1: 680; CHECK-DF2-NEXT: .p2align 2 681; CHECK-DF2-NEXT: .LCPI23_0: 682; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 683entry: 684 %fcmp = fcmp oeq double %x, 0.0 685 ret i1 %fcmp 686} 687 688;ord 689 690define i1 @FCMP_DOUBLE_ord(double %x, double %y) { 691; 692; 693; CHECK-DF-LABEL: FCMP_DOUBLE_ord: 694; CHECK-DF: # %bb.0: # %entry 695; CHECK-DF-NEXT: fcmpuod vr1, vr0 696; CHECK-DF-NEXT: mvcv16 a0 697; CHECK-DF-NEXT: rts16 698; 699; CHECK-DF2-LABEL: FCMP_DOUBLE_ord: 700; CHECK-DF2: # %bb.0: # %entry 701; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0 702; CHECK-DF2-NEXT: mvcv16 a0 703; CHECK-DF2-NEXT: rts16 704entry: 705 %fcmp = fcmp ord double %y, %x 706 ret i1 %fcmp 707} 708 709define i1 @FCMP_DOUBLE_I_ord(double %x) { 710; 711; 712; CHECK-DF-LABEL: FCMP_DOUBLE_I_ord: 713; CHECK-DF: # %bb.0: # %entry 714; CHECK-DF-NEXT: fcmpuod vr0, vr0 715; CHECK-DF-NEXT: mvcv16 a0 716; CHECK-DF-NEXT: rts16 717; 718; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ord: 719; CHECK-DF2: # %bb.0: # %entry 720; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr0 721; CHECK-DF2-NEXT: mvcv16 a0 722; CHECK-DF2-NEXT: rts16 723entry: 724 %fcmp = fcmp ord double %x, 0.0 725 ret i1 %fcmp 726} 727 728;uno 729 730define i1 @FCMP_DOUBLE_uno(double %x, double %y) { 731; 732; 733; CHECK-DF-LABEL: FCMP_DOUBLE_uno: 734; CHECK-DF: # %bb.0: # %entry 735; CHECK-DF-NEXT: fcmpuod vr1, vr0 736; CHECK-DF-NEXT: mvc32 a0 737; CHECK-DF-NEXT: rts16 738; 739; CHECK-DF2-LABEL: FCMP_DOUBLE_uno: 740; CHECK-DF2: # %bb.0: # %entry 741; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0 742; CHECK-DF2-NEXT: mvc32 a0 743; CHECK-DF2-NEXT: rts16 744entry: 745 %fcmp = fcmp uno double %y, %x 746 ret i1 %fcmp 747} 748 749define i1 @FCMP_DOUBLE_I_uno(double %x) { 750; 751; 752; CHECK-DF-LABEL: FCMP_DOUBLE_I_uno: 753; CHECK-DF: # %bb.0: # %entry 754; CHECK-DF-NEXT: fcmpuod vr0, vr0 755; CHECK-DF-NEXT: mvc32 a0 756; CHECK-DF-NEXT: rts16 757; 758; CHECK-DF2-LABEL: FCMP_DOUBLE_I_uno: 759; CHECK-DF2: # %bb.0: # %entry 760; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr0 761; CHECK-DF2-NEXT: mvc32 a0 762; CHECK-DF2-NEXT: rts16 763entry: 764 %fcmp = fcmp uno double %x, 0.0 765 ret i1 %fcmp 766} 767