xref: /llvm-project/llvm/test/CodeGen/CSKY/fpu/base-f.ll (revision 14e0a67a2d43b6e44032e8df788f43822da6fd71) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2
3; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF
4; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2
5
6
7define float @faddRR(float %x, float %y) {
8;
9; CHECK-SF-LABEL: faddRR:
10; CHECK-SF:       # %bb.0: # %entry
11; CHECK-SF-NEXT:    fadds vr0, vr1, vr0
12; CHECK-SF-NEXT:    rts16
13;
14; CHECK-SF2-LABEL: faddRR:
15; CHECK-SF2:       # %bb.0: # %entry
16; CHECK-SF2-NEXT:    fadd.32 vr0, vr1, vr0
17; CHECK-SF2-NEXT:    rts16
18
19entry:
20  %fadd = fadd  float %y, %x
21  ret float %fadd
22}
23
24define float @faddRI(float %x) {
25;
26; CHECK-SF-LABEL: faddRI:
27; CHECK-SF:       # %bb.0: # %entry
28; CHECK-SF-NEXT:    movih32 a0, 16672
29; CHECK-SF-NEXT:    fmtvrl vr1, a0
30; CHECK-SF-NEXT:    fadds vr0, vr0, vr1
31; CHECK-SF-NEXT:    rts16
32;
33; CHECK-SF2-LABEL: faddRI:
34; CHECK-SF2:       # %bb.0: # %entry
35; CHECK-SF2-NEXT:    movih32 a0, 16672
36; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
37; CHECK-SF2-NEXT:    fadd.32 vr0, vr0, vr1
38; CHECK-SF2-NEXT:    rts16
39
40entry:
41  %fadd = fadd  float %x, 10.0
42  ret float %fadd
43}
44
45define float @faddRI_X(float %x) {
46;
47; CHECK-SF-LABEL: faddRI_X:
48; CHECK-SF:       # %bb.0: # %entry
49; CHECK-SF-NEXT:    movih32 a0, 17792
50; CHECK-SF-NEXT:    ori32 a0, a0, 2048
51; CHECK-SF-NEXT:    fmtvrl vr1, a0
52; CHECK-SF-NEXT:    fadds vr0, vr0, vr1
53; CHECK-SF-NEXT:    rts16
54;
55; CHECK-SF2-LABEL: faddRI_X:
56; CHECK-SF2:       # %bb.0: # %entry
57; CHECK-SF2-NEXT:    movih32 a0, 17792
58; CHECK-SF2-NEXT:    ori32 a0, a0, 2048
59; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
60; CHECK-SF2-NEXT:    fadd.32 vr0, vr0, vr1
61; CHECK-SF2-NEXT:    rts16
62
63entry:
64  %fadd = fadd  float %x, 4097.0
65  ret float %fadd
66}
67
68define float @fsubRR(float %x, float %y) {
69;
70; CHECK-SF-LABEL: fsubRR:
71; CHECK-SF:       # %bb.0: # %entry
72; CHECK-SF-NEXT:    fsubs vr0, vr1, vr0
73; CHECK-SF-NEXT:    rts16
74;
75; CHECK-SF2-LABEL: fsubRR:
76; CHECK-SF2:       # %bb.0: # %entry
77; CHECK-SF2-NEXT:    fsub.32 vr0, vr1, vr0
78; CHECK-SF2-NEXT:    rts16
79
80
81entry:
82  %fsub = fsub  float %y, %x
83  ret float %fsub
84}
85
86define float @fsubRI(float %x) {
87;
88; CHECK-SF-LABEL: fsubRI:
89; CHECK-SF:       # %bb.0: # %entry
90; CHECK-SF-NEXT:    movih32 a0, 49440
91; CHECK-SF-NEXT:    fmtvrl vr1, a0
92; CHECK-SF-NEXT:    fadds vr0, vr0, vr1
93; CHECK-SF-NEXT:    rts16
94;
95; CHECK-SF2-LABEL: fsubRI:
96; CHECK-SF2:       # %bb.0: # %entry
97; CHECK-SF2-NEXT:    movih32 a0, 49440
98; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
99; CHECK-SF2-NEXT:    fadd.32 vr0, vr0, vr1
100; CHECK-SF2-NEXT:    rts16
101
102entry:
103  %fsub = fsub  float %x, 10.0
104  ret float %fsub
105}
106
107define float @fsubRI_X(float %x) {
108;
109; CHECK-SF-LABEL: fsubRI_X:
110; CHECK-SF:       # %bb.0: # %entry
111; CHECK-SF-NEXT:    movih32 a0, 50560
112; CHECK-SF-NEXT:    ori32 a0, a0, 2048
113; CHECK-SF-NEXT:    fmtvrl vr1, a0
114; CHECK-SF-NEXT:    fadds vr0, vr0, vr1
115; CHECK-SF-NEXT:    rts16
116;
117; CHECK-SF2-LABEL: fsubRI_X:
118; CHECK-SF2:       # %bb.0: # %entry
119; CHECK-SF2-NEXT:    movih32 a0, 50560
120; CHECK-SF2-NEXT:    ori32 a0, a0, 2048
121; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
122; CHECK-SF2-NEXT:    fadd.32 vr0, vr0, vr1
123; CHECK-SF2-NEXT:    rts16
124
125entry:
126  %fsub = fsub  float %x, 4097.0
127  ret float %fsub
128}
129
130define float @fmulRR(float %x, float %y) {
131;
132; CHECK-SF-LABEL: fmulRR:
133; CHECK-SF:       # %bb.0: # %entry
134; CHECK-SF-NEXT:    fmuls vr0, vr1, vr0
135; CHECK-SF-NEXT:    rts16
136;
137; CHECK-SF2-LABEL: fmulRR:
138; CHECK-SF2:       # %bb.0: # %entry
139; CHECK-SF2-NEXT:    fmul.32 vr0, vr1, vr0
140; CHECK-SF2-NEXT:    rts16
141
142entry:
143  %fmul = fmul  float %y, %x
144  ret float %fmul
145}
146
147define float @fnmulRR_a(float %x, float %y) {
148;
149; CHECK-SF-LABEL: fnmulRR_a:
150; CHECK-SF:       # %bb.0: # %entry
151; CHECK-SF-NEXT:    fnmuls vr0, vr1, vr0
152; CHECK-SF-NEXT:    rts16
153;
154; CHECK-SF2-LABEL: fnmulRR_a:
155; CHECK-SF2:       # %bb.0: # %entry
156; CHECK-SF2-NEXT:    fnmul.32 vr0, vr1, vr0
157; CHECK-SF2-NEXT:    rts16
158
159entry:
160  %z = fneg float %y
161  %fnmul = fmul float %z, %x
162  ret float %fnmul
163}
164
165define float @fnmulRR_b(float %x, float %y) {
166; CHECK-SF-LABEL: fnmulRR_b:
167; CHECK-SF:       # %bb.0: # %entry
168; CHECK-SF-NEXT:    fnmuls vr0, vr0, vr1
169; CHECK-SF-NEXT:    rts16
170;
171; CHECK-SF2-LABEL: fnmulRR_b:
172; CHECK-SF2:       # %bb.0: # %entry
173; CHECK-SF2-NEXT:    fnmul.32 vr0, vr0, vr1
174; CHECK-SF2-NEXT:    rts16
175entry:
176  %z = fneg float %x
177  %fnmul = fmul float %y, %z
178  ret float %fnmul
179}
180
181define float @fmulRI(float %x) {
182;
183; CHECK-SF-LABEL: fmulRI:
184; CHECK-SF:       # %bb.0: # %entry
185; CHECK-SF-NEXT:    movih32 a0, 16672
186; CHECK-SF-NEXT:    fmtvrl vr1, a0
187; CHECK-SF-NEXT:    fmuls vr0, vr0, vr1
188; CHECK-SF-NEXT:    rts16
189;
190; CHECK-SF2-LABEL: fmulRI:
191; CHECK-SF2:       # %bb.0: # %entry
192; CHECK-SF2-NEXT:    movih32 a0, 16672
193; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
194; CHECK-SF2-NEXT:    fmul.32 vr0, vr0, vr1
195; CHECK-SF2-NEXT:    rts16
196
197entry:
198  %fmul = fmul  float %x, 10.0
199  ret float %fmul
200}
201
202define float @fmulRI_X(float %x) {
203;
204; CHECK-SF-LABEL: fmulRI_X:
205; CHECK-SF:       # %bb.0: # %entry
206; CHECK-SF-NEXT:    movih32 a0, 17792
207; CHECK-SF-NEXT:    ori32 a0, a0, 2048
208; CHECK-SF-NEXT:    fmtvrl vr1, a0
209; CHECK-SF-NEXT:    fmuls vr0, vr0, vr1
210; CHECK-SF-NEXT:    rts16
211;
212; CHECK-SF2-LABEL: fmulRI_X:
213; CHECK-SF2:       # %bb.0: # %entry
214; CHECK-SF2-NEXT:    movih32 a0, 17792
215; CHECK-SF2-NEXT:    ori32 a0, a0, 2048
216; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
217; CHECK-SF2-NEXT:    fmul.32 vr0, vr0, vr1
218; CHECK-SF2-NEXT:    rts16
219
220entry:
221  %fmul = fmul  float %x, 4097.0
222  ret float %fmul
223}
224
225define float @fdivRR(float %x, float %y) {
226;
227; CHECK-SF-LABEL: fdivRR:
228; CHECK-SF:       # %bb.0: # %entry
229; CHECK-SF-NEXT:    fdivs vr0, vr1, vr0
230; CHECK-SF-NEXT:    rts16
231;
232; CHECK-SF2-LABEL: fdivRR:
233; CHECK-SF2:       # %bb.0: # %entry
234; CHECK-SF2-NEXT:    fdiv.32 vr0, vr1, vr0
235; CHECK-SF2-NEXT:    rts16
236
237
238entry:
239  %fdiv = fdiv  float %y, %x
240  ret float %fdiv
241}
242
243define float @fdivRI(float %x) {
244;
245; CHECK-SF-LABEL: fdivRI:
246; CHECK-SF:       # %bb.0: # %entry
247; CHECK-SF-NEXT:    movih32 a0, 16672
248; CHECK-SF-NEXT:    fmtvrl vr1, a0
249; CHECK-SF-NEXT:    fdivs vr0, vr0, vr1
250; CHECK-SF-NEXT:    rts16
251;
252; CHECK-SF2-LABEL: fdivRI:
253; CHECK-SF2:       # %bb.0: # %entry
254; CHECK-SF2-NEXT:    movih32 a0, 16672
255; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
256; CHECK-SF2-NEXT:    fdiv.32 vr0, vr0, vr1
257; CHECK-SF2-NEXT:    rts16
258
259
260entry:
261  %fdiv = fdiv  float %x, 10.0
262  ret float %fdiv
263}
264
265define float @fdivRI_X(float %x) {
266;
267; CHECK-SF-LABEL: fdivRI_X:
268; CHECK-SF:       # %bb.0: # %entry
269; CHECK-SF-NEXT:    movih32 a0, 17792
270; CHECK-SF-NEXT:    ori32 a0, a0, 2048
271; CHECK-SF-NEXT:    fmtvrl vr1, a0
272; CHECK-SF-NEXT:    fdivs vr0, vr0, vr1
273; CHECK-SF-NEXT:    rts16
274;
275; CHECK-SF2-LABEL: fdivRI_X:
276; CHECK-SF2:       # %bb.0: # %entry
277; CHECK-SF2-NEXT:    movih32 a0, 17792
278; CHECK-SF2-NEXT:    ori32 a0, a0, 2048
279; CHECK-SF2-NEXT:    fmtvr.32.1 vr1, a0
280; CHECK-SF2-NEXT:    fdiv.32 vr0, vr0, vr1
281; CHECK-SF2-NEXT:    rts16
282
283entry:
284  %fdiv = fdiv  float %x, 4097.0
285  ret float %fdiv
286}
287
288define float @fnegRR(float %x) {
289;
290; CHECK-SF-LABEL: fnegRR:
291; CHECK-SF:       # %bb.0: # %entry
292; CHECK-SF-NEXT:    fnegs vr0, vr0
293; CHECK-SF-NEXT:    rts16
294;
295; CHECK-SF2-LABEL: fnegRR:
296; CHECK-SF2:       # %bb.0: # %entry
297; CHECK-SF2-NEXT:    fneg.32 vr0, vr0
298; CHECK-SF2-NEXT:    rts16
299
300entry:
301  %fneg = fneg  float %x
302  ret float %fneg
303}
304