xref: /llvm-project/llvm/test/CodeGen/CSKY/bseti_bclri.ll (revision 528831dd1ada271d1ae52eef2803ba0996efc324) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 < %s -mtriple=csky | FileCheck %s
3
4define i32 @test_or_128(i32 noundef %0) {
5; CHECK-LABEL: test_or_128:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    ori32 a0, a0, 128
8; CHECK-NEXT:    rts16
9 %2 = or i32 %0, 128
10 ret i32 %2
11}
12
13define i32 @test_or_131072(i32 noundef %0) {
14; CHECK-LABEL: test_or_131072:
15; CHECK:       # %bb.0:
16; CHECK-NEXT:    bseti16 a0, 17
17; CHECK-NEXT:    rts16
18 %2 = or i32 %0, 131072
19 ret i32 %2
20}
21
22define i32 @test_or_192(i32 noundef %0) {
23; CHECK-LABEL: test_or_192:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    ori32 a0, a0, 192
26; CHECK-NEXT:    rts16
27 %2 = or i32 %0, 192
28 ret i32 %2
29}
30
31define i32 @test_or_3072(i32 noundef %0) {
32; CHECK-LABEL: test_or_3072:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    ori32 a0, a0, 3072
35; CHECK-NEXT:    rts16
36 %2 = or i32 %0, 3072
37 ret i32 %2
38}
39
40define i32 @test_or_196608(i32 noundef %0) {
41; CHECK-LABEL: test_or_196608:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    movih32 a1, 3
44; CHECK-NEXT:    or16 a0, a1
45; CHECK-NEXT:    rts16
46 %2 = or i32 %0, 196608
47 ret i32 %2
48}
49
50define i32 @test_or_65540(i32 noundef %0) {
51; CHECK-LABEL: test_or_65540:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    movih32 a1, 1
54; CHECK-NEXT:    ori32 a1, a1, 4
55; CHECK-NEXT:    or16 a0, a1
56; CHECK-NEXT:    rts16
57 %2 = or i32 %0, 65540
58 ret i32 %2
59}
60
61define i32 @test_andnot_128(i32 noundef %0) {
62; CHECK-LABEL: test_andnot_128:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    andni32 a0, a0, 128
65; CHECK-NEXT:    rts16
66 %2 = and i32 %0, -129
67 ret i32 %2
68}
69
70define i32 @test_andnot_131072(i32 noundef %0) {
71; CHECK-LABEL: test_andnot_131072:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    bclri16 a0, 17
74; CHECK-NEXT:    rts16
75 %2 = and i32 %0, -131073
76 ret i32 %2
77}
78
79define i32 @test_andnot_192(i32 noundef %0) {
80; CHECK-LABEL: test_andnot_192:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    andni32 a0, a0, 192
83; CHECK-NEXT:    rts16
84 %2 = and i32 %0, -193
85 ret i32 %2
86}
87
88define i32 @test_andnot_3072(i32 noundef %0) {
89; CHECK-LABEL: test_andnot_3072:
90; CHECK:       # %bb.0:
91; CHECK-NEXT:    andni32 a0, a0, 3072
92; CHECK-NEXT:    rts16
93 %2 = and i32 %0, -3073
94 ret i32 %2
95}
96
97define i32 @test_andnot_1966608(i32 noundef %0) {
98; CHECK-LABEL: test_andnot_1966608:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    movih32 a1, 65505
101; CHECK-NEXT:    ori32 a1, a1, 65007
102; CHECK-NEXT:    and16 a0, a1
103; CHECK-NEXT:    rts16
104 %2 = and i32 %0, -1966609
105 ret i32 %2
106}
107
108define i32 @test_andnot_65540(i32 noundef %0) {
109; CHECK-LABEL: test_andnot_65540:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    movih32 a1, 65534
112; CHECK-NEXT:    ori32 a1, a1, 65531
113; CHECK-NEXT:    and16 a0, a1
114; CHECK-NEXT:    rts16
115 %2 = and i32 %0, -65541
116 ret i32 %2
117}
118