1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -O1 -mtriple arm -o - %s | FileCheck --check-prefix CHECK-LE %s 3; RUN: llc -O1 -mtriple armv7 -o - %s | FileCheck --check-prefix CHECK-V7-LE %s 4; RUN: llc -O1 -mtriple armeb -o - %s | FileCheck --check-prefix CHECK-BE %s 5; RUN: llc -O1 -mtriple armv7eb -o - %s | FileCheck --check-prefix CHECK-V7-BE %s 6 7; A collection of regression tests to verify the load-narrowing part of 8; TargetLowering::SimplifySetCC (and/or other similar rewrites such as 9; combining AND+LOAD into ZEXTLOAD). 10; 11; Using both arm and armv7 to show that alignment restrictions are 12; considered for the narrowed load (armv7 is a bit more relaxed when it 13; comes to unaligned memory accesses). 14 15;-------------------------------------------------------------------------- 16; Test non byte-sized types. 17; 18; As long as LLVM IR isn't defining where the padding goes we can't really 19; optimize these (without adding a target lowering hook that can inform 20; ISel about which bits are padding). 21; -------------------------------------------------------------------------- 22 23define i1 @test_129_15_0(ptr %y) { 24; CHECK-LE-LABEL: test_129_15_0: 25; CHECK-LE: @ %bb.0: 26; CHECK-LE-NEXT: ldrh r0, [r0] 27; CHECK-LE-NEXT: mov r1, #255 28; CHECK-LE-NEXT: orr r1, r1, #32512 29; CHECK-LE-NEXT: ands r0, r0, r1 30; CHECK-LE-NEXT: movne r0, #1 31; CHECK-LE-NEXT: mov pc, lr 32; 33; CHECK-V7-LE-LABEL: test_129_15_0: 34; CHECK-V7-LE: @ %bb.0: 35; CHECK-V7-LE-NEXT: ldrh r0, [r0] 36; CHECK-V7-LE-NEXT: bfc r0, #15, #17 37; CHECK-V7-LE-NEXT: cmp r0, #0 38; CHECK-V7-LE-NEXT: movwne r0, #1 39; CHECK-V7-LE-NEXT: bx lr 40; 41; CHECK-BE-LABEL: test_129_15_0: 42; CHECK-BE: @ %bb.0: 43; CHECK-BE-NEXT: ldr r1, [r0, #12] 44; CHECK-BE-NEXT: ldrb r0, [r0, #16] 45; CHECK-BE-NEXT: orr r0, r0, r1, lsl #8 46; CHECK-BE-NEXT: mov r1, #255 47; CHECK-BE-NEXT: orr r1, r1, #32512 48; CHECK-BE-NEXT: ands r0, r0, r1 49; CHECK-BE-NEXT: movne r0, #1 50; CHECK-BE-NEXT: mov pc, lr 51; 52; CHECK-V7-BE-LABEL: test_129_15_0: 53; CHECK-V7-BE: @ %bb.0: 54; CHECK-V7-BE-NEXT: ldrh r0, [r0, #15] 55; CHECK-V7-BE-NEXT: bfc r0, #15, #17 56; CHECK-V7-BE-NEXT: cmp r0, #0 57; CHECK-V7-BE-NEXT: movwne r0, #1 58; CHECK-V7-BE-NEXT: bx lr 59 %a = load i129, ptr %y 60 %b = and i129 %a, u0x7fff 61 %cmp = icmp ne i129 %b, 0 62 ret i1 %cmp 63} 64 65define i1 @test_126_20_4(ptr %y) { 66; CHECK-LE-LABEL: test_126_20_4: 67; CHECK-LE: @ %bb.0: 68; CHECK-LE-NEXT: ldr r0, [r0] 69; CHECK-LE-NEXT: mvn r1, #15 70; CHECK-LE-NEXT: sub r1, r1, #-16777216 71; CHECK-LE-NEXT: ands r0, r0, r1 72; CHECK-LE-NEXT: movne r0, #1 73; CHECK-LE-NEXT: mov pc, lr 74; 75; CHECK-V7-LE-LABEL: test_126_20_4: 76; CHECK-V7-LE: @ %bb.0: 77; CHECK-V7-LE-NEXT: ldr r0, [r0] 78; CHECK-V7-LE-NEXT: movw r1, #65520 79; CHECK-V7-LE-NEXT: movt r1, #255 80; CHECK-V7-LE-NEXT: ands r0, r0, r1 81; CHECK-V7-LE-NEXT: movwne r0, #1 82; CHECK-V7-LE-NEXT: bx lr 83; 84; CHECK-BE-LABEL: test_126_20_4: 85; CHECK-BE: @ %bb.0: 86; CHECK-BE-NEXT: ldr r0, [r0, #12] 87; CHECK-BE-NEXT: mvn r1, #15 88; CHECK-BE-NEXT: sub r1, r1, #-16777216 89; CHECK-BE-NEXT: ands r0, r0, r1 90; CHECK-BE-NEXT: movne r0, #1 91; CHECK-BE-NEXT: mov pc, lr 92; 93; CHECK-V7-BE-LABEL: test_126_20_4: 94; CHECK-V7-BE: @ %bb.0: 95; CHECK-V7-BE-NEXT: ldr r0, [r0, #12] 96; CHECK-V7-BE-NEXT: movw r1, #65520 97; CHECK-V7-BE-NEXT: movt r1, #255 98; CHECK-V7-BE-NEXT: ands r0, r0, r1 99; CHECK-V7-BE-NEXT: movwne r0, #1 100; CHECK-V7-BE-NEXT: bx lr 101 %a = load i126, ptr %y 102 %b = and i126 %a, u0xfffff0 103 %cmp = icmp ne i126 %b, 0 104 ret i1 %cmp 105} 106 107define i1 @test_33_8_0(ptr %y) { 108; CHECK-LE-LABEL: test_33_8_0: 109; CHECK-LE: @ %bb.0: 110; CHECK-LE-NEXT: ldrb r0, [r0] 111; CHECK-LE-NEXT: cmp r0, #0 112; CHECK-LE-NEXT: movne r0, #1 113; CHECK-LE-NEXT: mov pc, lr 114; 115; CHECK-V7-LE-LABEL: test_33_8_0: 116; CHECK-V7-LE: @ %bb.0: 117; CHECK-V7-LE-NEXT: ldrb r0, [r0] 118; CHECK-V7-LE-NEXT: cmp r0, #0 119; CHECK-V7-LE-NEXT: movwne r0, #1 120; CHECK-V7-LE-NEXT: bx lr 121; 122; CHECK-BE-LABEL: test_33_8_0: 123; CHECK-BE: @ %bb.0: 124; CHECK-BE-NEXT: ldrb r0, [r0, #4] 125; CHECK-BE-NEXT: cmp r0, #0 126; CHECK-BE-NEXT: movne r0, #1 127; CHECK-BE-NEXT: mov pc, lr 128; 129; CHECK-V7-BE-LABEL: test_33_8_0: 130; CHECK-V7-BE: @ %bb.0: 131; CHECK-V7-BE-NEXT: ldrb r0, [r0, #4] 132; CHECK-V7-BE-NEXT: cmp r0, #0 133; CHECK-V7-BE-NEXT: movwne r0, #1 134; CHECK-V7-BE-NEXT: bx lr 135 %a = load i33, ptr %y 136 %b = and i33 %a, u0xff 137 %cmp = icmp ne i33 %b, 0 138 ret i1 %cmp 139} 140 141define i1 @test_33_1_32(ptr %y) { 142; CHECK-LE-LABEL: test_33_1_32: 143; CHECK-LE: @ %bb.0: 144; CHECK-LE-NEXT: ldrb r0, [r0, #4] 145; CHECK-LE-NEXT: mov pc, lr 146; 147; CHECK-V7-LE-LABEL: test_33_1_32: 148; CHECK-V7-LE: @ %bb.0: 149; CHECK-V7-LE-NEXT: ldrb r0, [r0, #4] 150; CHECK-V7-LE-NEXT: bx lr 151; 152; CHECK-BE-LABEL: test_33_1_32: 153; CHECK-BE: @ %bb.0: 154; CHECK-BE-NEXT: ldr r0, [r0] 155; CHECK-BE-NEXT: lsr r0, r0, #24 156; CHECK-BE-NEXT: mov pc, lr 157; 158; CHECK-V7-BE-LABEL: test_33_1_32: 159; CHECK-V7-BE: @ %bb.0: 160; CHECK-V7-BE-NEXT: ldr r0, [r0] 161; CHECK-V7-BE-NEXT: lsr r0, r0, #24 162; CHECK-V7-BE-NEXT: bx lr 163 %a = load i33, ptr %y 164 %b = and i33 %a, u0x100000000 165 %cmp = icmp ne i33 %b, 0 166 ret i1 %cmp 167} 168 169define i1 @test_33_1_31(ptr %y) { 170; CHECK-LE-LABEL: test_33_1_31: 171; CHECK-LE: @ %bb.0: 172; CHECK-LE-NEXT: ldrb r0, [r0, #3] 173; CHECK-LE-NEXT: lsr r0, r0, #7 174; CHECK-LE-NEXT: mov pc, lr 175; 176; CHECK-V7-LE-LABEL: test_33_1_31: 177; CHECK-V7-LE: @ %bb.0: 178; CHECK-V7-LE-NEXT: ldrb r0, [r0, #3] 179; CHECK-V7-LE-NEXT: lsr r0, r0, #7 180; CHECK-V7-LE-NEXT: bx lr 181; 182; CHECK-BE-LABEL: test_33_1_31: 183; CHECK-BE: @ %bb.0: 184; CHECK-BE-NEXT: ldrb r0, [r0, #1] 185; CHECK-BE-NEXT: lsr r0, r0, #7 186; CHECK-BE-NEXT: mov pc, lr 187; 188; CHECK-V7-BE-LABEL: test_33_1_31: 189; CHECK-V7-BE: @ %bb.0: 190; CHECK-V7-BE-NEXT: ldrb r0, [r0, #1] 191; CHECK-V7-BE-NEXT: lsr r0, r0, #7 192; CHECK-V7-BE-NEXT: bx lr 193 %a = load i33, ptr %y 194 %b = and i33 %a, u0x80000000 195 %cmp = icmp ne i33 %b, 0 196 ret i1 %cmp 197} 198 199define i1 @test_33_1_0(ptr %y) { 200; CHECK-LE-LABEL: test_33_1_0: 201; CHECK-LE: @ %bb.0: 202; CHECK-LE-NEXT: ldrb r0, [r0] 203; CHECK-LE-NEXT: and r0, r0, #1 204; CHECK-LE-NEXT: mov pc, lr 205; 206; CHECK-V7-LE-LABEL: test_33_1_0: 207; CHECK-V7-LE: @ %bb.0: 208; CHECK-V7-LE-NEXT: ldrb r0, [r0] 209; CHECK-V7-LE-NEXT: and r0, r0, #1 210; CHECK-V7-LE-NEXT: bx lr 211; 212; CHECK-BE-LABEL: test_33_1_0: 213; CHECK-BE: @ %bb.0: 214; CHECK-BE-NEXT: ldrb r0, [r0, #4] 215; CHECK-BE-NEXT: and r0, r0, #1 216; CHECK-BE-NEXT: mov pc, lr 217; 218; CHECK-V7-BE-LABEL: test_33_1_0: 219; CHECK-V7-BE: @ %bb.0: 220; CHECK-V7-BE-NEXT: ldrb r0, [r0, #4] 221; CHECK-V7-BE-NEXT: and r0, r0, #1 222; CHECK-V7-BE-NEXT: bx lr 223 %a = load i33, ptr %y 224 %b = and i33 %a, u0x1 225 %cmp = icmp ne i33 %b, 0 226 ret i1 %cmp 227} 228 229;-------------------------------------------------------------------------- 230; Test byte-sized types. 231;-------------------------------------------------------------------------- 232 233 234define i1 @test_128_20_4(ptr %y) { 235; CHECK-LE-LABEL: test_128_20_4: 236; CHECK-LE: @ %bb.0: 237; CHECK-LE-NEXT: ldr r0, [r0] 238; CHECK-LE-NEXT: mvn r1, #15 239; CHECK-LE-NEXT: sub r1, r1, #-16777216 240; CHECK-LE-NEXT: ands r0, r0, r1 241; CHECK-LE-NEXT: movne r0, #1 242; CHECK-LE-NEXT: mov pc, lr 243; 244; CHECK-V7-LE-LABEL: test_128_20_4: 245; CHECK-V7-LE: @ %bb.0: 246; CHECK-V7-LE-NEXT: ldr r0, [r0] 247; CHECK-V7-LE-NEXT: movw r1, #65520 248; CHECK-V7-LE-NEXT: movt r1, #255 249; CHECK-V7-LE-NEXT: ands r0, r0, r1 250; CHECK-V7-LE-NEXT: movwne r0, #1 251; CHECK-V7-LE-NEXT: bx lr 252; 253; CHECK-BE-LABEL: test_128_20_4: 254; CHECK-BE: @ %bb.0: 255; CHECK-BE-NEXT: ldr r0, [r0, #12] 256; CHECK-BE-NEXT: mvn r1, #15 257; CHECK-BE-NEXT: sub r1, r1, #-16777216 258; CHECK-BE-NEXT: ands r0, r0, r1 259; CHECK-BE-NEXT: movne r0, #1 260; CHECK-BE-NEXT: mov pc, lr 261; 262; CHECK-V7-BE-LABEL: test_128_20_4: 263; CHECK-V7-BE: @ %bb.0: 264; CHECK-V7-BE-NEXT: ldr r0, [r0, #12] 265; CHECK-V7-BE-NEXT: movw r1, #65520 266; CHECK-V7-BE-NEXT: movt r1, #255 267; CHECK-V7-BE-NEXT: ands r0, r0, r1 268; CHECK-V7-BE-NEXT: movwne r0, #1 269; CHECK-V7-BE-NEXT: bx lr 270 %a = load i128, ptr %y 271 %b = and i128 %a, u0xfffff0 272 %cmp = icmp ne i128 %b, 0 273 ret i1 %cmp 274} 275 276define i1 @test_48_16_0(ptr %y) { 277; CHECK-LE-LABEL: test_48_16_0: 278; CHECK-LE: @ %bb.0: 279; CHECK-LE-NEXT: ldrh r0, [r0] 280; CHECK-LE-NEXT: cmp r0, #0 281; CHECK-LE-NEXT: movne r0, #1 282; CHECK-LE-NEXT: mov pc, lr 283; 284; CHECK-V7-LE-LABEL: test_48_16_0: 285; CHECK-V7-LE: @ %bb.0: 286; CHECK-V7-LE-NEXT: ldrh r0, [r0] 287; CHECK-V7-LE-NEXT: cmp r0, #0 288; CHECK-V7-LE-NEXT: movwne r0, #1 289; CHECK-V7-LE-NEXT: bx lr 290; 291; CHECK-BE-LABEL: test_48_16_0: 292; CHECK-BE: @ %bb.0: 293; CHECK-BE-NEXT: ldrh r0, [r0, #4] 294; CHECK-BE-NEXT: cmp r0, #0 295; CHECK-BE-NEXT: movne r0, #1 296; CHECK-BE-NEXT: mov pc, lr 297; 298; CHECK-V7-BE-LABEL: test_48_16_0: 299; CHECK-V7-BE: @ %bb.0: 300; CHECK-V7-BE-NEXT: ldrh r0, [r0, #4] 301; CHECK-V7-BE-NEXT: cmp r0, #0 302; CHECK-V7-BE-NEXT: movwne r0, #1 303; CHECK-V7-BE-NEXT: bx lr 304 %a = load i48, ptr %y 305 %b = and i48 %a, u0xffff 306 %cmp = icmp ne i48 %b, 0 307 ret i1 %cmp 308} 309 310define i1 @test_48_16_8(ptr %y) { 311; CHECK-LE-LABEL: test_48_16_8: 312; CHECK-LE: @ %bb.0: 313; CHECK-LE-NEXT: ldrh r0, [r0, #1] 314; CHECK-LE-NEXT: lsls r0, r0, #8 315; CHECK-LE-NEXT: movne r0, #1 316; CHECK-LE-NEXT: mov pc, lr 317; 318; CHECK-V7-LE-LABEL: test_48_16_8: 319; CHECK-V7-LE: @ %bb.0: 320; CHECK-V7-LE-NEXT: ldrh r0, [r0, #1] 321; CHECK-V7-LE-NEXT: cmp r0, #0 322; CHECK-V7-LE-NEXT: movwne r0, #1 323; CHECK-V7-LE-NEXT: bx lr 324; 325; CHECK-BE-LABEL: test_48_16_8: 326; CHECK-BE: @ %bb.0: 327; CHECK-BE-NEXT: ldrh r0, [r0, #3] 328; CHECK-BE-NEXT: cmp r0, #0 329; CHECK-BE-NEXT: movne r0, #1 330; CHECK-BE-NEXT: mov pc, lr 331; 332; CHECK-V7-BE-LABEL: test_48_16_8: 333; CHECK-V7-BE: @ %bb.0: 334; CHECK-V7-BE-NEXT: ldrh r0, [r0, #3] 335; CHECK-V7-BE-NEXT: cmp r0, #0 336; CHECK-V7-BE-NEXT: movwne r0, #1 337; CHECK-V7-BE-NEXT: bx lr 338 %a = load i48, ptr %y 339 %b = and i48 %a, u0xffff00 340 %cmp = icmp ne i48 %b, 0 341 ret i1 %cmp 342} 343 344define i1 @test_48_16_16(ptr %y) { 345; CHECK-LE-LABEL: test_48_16_16: 346; CHECK-LE: @ %bb.0: 347; CHECK-LE-NEXT: ldrh r0, [r0, #2] 348; CHECK-LE-NEXT: cmp r0, #0 349; CHECK-LE-NEXT: movne r0, #1 350; CHECK-LE-NEXT: mov pc, lr 351; 352; CHECK-V7-LE-LABEL: test_48_16_16: 353; CHECK-V7-LE: @ %bb.0: 354; CHECK-V7-LE-NEXT: ldrh r0, [r0, #2] 355; CHECK-V7-LE-NEXT: cmp r0, #0 356; CHECK-V7-LE-NEXT: movwne r0, #1 357; CHECK-V7-LE-NEXT: bx lr 358; 359; CHECK-BE-LABEL: test_48_16_16: 360; CHECK-BE: @ %bb.0: 361; CHECK-BE-NEXT: ldrh r0, [r0, #2] 362; CHECK-BE-NEXT: cmp r0, #0 363; CHECK-BE-NEXT: movne r0, #1 364; CHECK-BE-NEXT: mov pc, lr 365; 366; CHECK-V7-BE-LABEL: test_48_16_16: 367; CHECK-V7-BE: @ %bb.0: 368; CHECK-V7-BE-NEXT: ldrh r0, [r0, #2] 369; CHECK-V7-BE-NEXT: cmp r0, #0 370; CHECK-V7-BE-NEXT: movwne r0, #1 371; CHECK-V7-BE-NEXT: bx lr 372 %a = load i48, ptr %y 373 %b = and i48 %a, u0xffff0000 374 %cmp = icmp ne i48 %b, 0 375 ret i1 %cmp 376} 377 378define i1 @test_48_16_32(ptr %y) { 379; CHECK-LE-LABEL: test_48_16_32: 380; CHECK-LE: @ %bb.0: 381; CHECK-LE-NEXT: ldrh r0, [r0, #4] 382; CHECK-LE-NEXT: cmp r0, #0 383; CHECK-LE-NEXT: movne r0, #1 384; CHECK-LE-NEXT: mov pc, lr 385; 386; CHECK-V7-LE-LABEL: test_48_16_32: 387; CHECK-V7-LE: @ %bb.0: 388; CHECK-V7-LE-NEXT: ldrh r0, [r0, #4] 389; CHECK-V7-LE-NEXT: cmp r0, #0 390; CHECK-V7-LE-NEXT: movwne r0, #1 391; CHECK-V7-LE-NEXT: bx lr 392; 393; CHECK-BE-LABEL: test_48_16_32: 394; CHECK-BE: @ %bb.0: 395; CHECK-BE-NEXT: ldrh r0, [r0] 396; CHECK-BE-NEXT: cmp r0, #0 397; CHECK-BE-NEXT: movne r0, #1 398; CHECK-BE-NEXT: mov pc, lr 399; 400; CHECK-V7-BE-LABEL: test_48_16_32: 401; CHECK-V7-BE: @ %bb.0: 402; CHECK-V7-BE-NEXT: ldrh r0, [r0] 403; CHECK-V7-BE-NEXT: cmp r0, #0 404; CHECK-V7-BE-NEXT: movwne r0, #1 405; CHECK-V7-BE-NEXT: bx lr 406 %a = load i48, ptr %y 407 %b = and i48 %a, u0xffff00000000 408 %cmp = icmp ne i48 %b, 0 409 ret i1 %cmp 410} 411 412define i1 @test_48_17_0(ptr %y) { 413; CHECK-LE-LABEL: test_48_17_0: 414; CHECK-LE: @ %bb.0: 415; CHECK-LE-NEXT: ldr r0, [r0] 416; CHECK-LE-NEXT: ldr r1, .LCPI11_0 417; CHECK-LE-NEXT: ands r0, r0, r1 418; CHECK-LE-NEXT: movne r0, #1 419; CHECK-LE-NEXT: mov pc, lr 420; CHECK-LE-NEXT: .p2align 2 421; CHECK-LE-NEXT: @ %bb.1: 422; CHECK-LE-NEXT: .LCPI11_0: 423; CHECK-LE-NEXT: .long 131071 @ 0x1ffff 424; 425; CHECK-V7-LE-LABEL: test_48_17_0: 426; CHECK-V7-LE: @ %bb.0: 427; CHECK-V7-LE-NEXT: ldr r0, [r0] 428; CHECK-V7-LE-NEXT: bfc r0, #17, #15 429; CHECK-V7-LE-NEXT: cmp r0, #0 430; CHECK-V7-LE-NEXT: movwne r0, #1 431; CHECK-V7-LE-NEXT: bx lr 432; 433; CHECK-BE-LABEL: test_48_17_0: 434; CHECK-BE: @ %bb.0: 435; CHECK-BE-NEXT: ldr r1, [r0] 436; CHECK-BE-NEXT: ldrh r0, [r0, #4] 437; CHECK-BE-NEXT: orr r0, r0, r1, lsl #16 438; CHECK-BE-NEXT: ldr r1, .LCPI11_0 439; CHECK-BE-NEXT: ands r0, r0, r1 440; CHECK-BE-NEXT: movne r0, #1 441; CHECK-BE-NEXT: mov pc, lr 442; CHECK-BE-NEXT: .p2align 2 443; CHECK-BE-NEXT: @ %bb.1: 444; CHECK-BE-NEXT: .LCPI11_0: 445; CHECK-BE-NEXT: .long 131071 @ 0x1ffff 446; 447; CHECK-V7-BE-LABEL: test_48_17_0: 448; CHECK-V7-BE: @ %bb.0: 449; CHECK-V7-BE-NEXT: ldr r0, [r0, #2] 450; CHECK-V7-BE-NEXT: bfc r0, #17, #15 451; CHECK-V7-BE-NEXT: cmp r0, #0 452; CHECK-V7-BE-NEXT: movwne r0, #1 453; CHECK-V7-BE-NEXT: bx lr 454 %a = load i48, ptr %y 455 %b = and i48 %a, u0x1ffff 456 %cmp = icmp ne i48 %b, 0 457 ret i1 %cmp 458} 459 460define i1 @test_40_16_0(ptr %y) { 461; CHECK-LE-LABEL: test_40_16_0: 462; CHECK-LE: @ %bb.0: 463; CHECK-LE-NEXT: ldrh r0, [r0] 464; CHECK-LE-NEXT: cmp r0, #0 465; CHECK-LE-NEXT: movne r0, #1 466; CHECK-LE-NEXT: mov pc, lr 467; 468; CHECK-V7-LE-LABEL: test_40_16_0: 469; CHECK-V7-LE: @ %bb.0: 470; CHECK-V7-LE-NEXT: ldrh r0, [r0] 471; CHECK-V7-LE-NEXT: cmp r0, #0 472; CHECK-V7-LE-NEXT: movwne r0, #1 473; CHECK-V7-LE-NEXT: bx lr 474; 475; CHECK-BE-LABEL: test_40_16_0: 476; CHECK-BE: @ %bb.0: 477; CHECK-BE-NEXT: ldrh r0, [r0, #3] 478; CHECK-BE-NEXT: cmp r0, #0 479; CHECK-BE-NEXT: movne r0, #1 480; CHECK-BE-NEXT: mov pc, lr 481; 482; CHECK-V7-BE-LABEL: test_40_16_0: 483; CHECK-V7-BE: @ %bb.0: 484; CHECK-V7-BE-NEXT: ldrh r0, [r0, #3] 485; CHECK-V7-BE-NEXT: cmp r0, #0 486; CHECK-V7-BE-NEXT: movwne r0, #1 487; CHECK-V7-BE-NEXT: bx lr 488 %a = load i40, ptr %y 489 %b = and i40 %a, u0xffff 490 %cmp = icmp ne i40 %b, 0 491 ret i1 %cmp 492} 493 494define i1 @test_40_1_32(ptr %y) { 495; CHECK-LE-LABEL: test_40_1_32: 496; CHECK-LE: @ %bb.0: 497; CHECK-LE-NEXT: ldrb r0, [r0, #4] 498; CHECK-LE-NEXT: and r0, r0, #1 499; CHECK-LE-NEXT: mov pc, lr 500; 501; CHECK-V7-LE-LABEL: test_40_1_32: 502; CHECK-V7-LE: @ %bb.0: 503; CHECK-V7-LE-NEXT: ldrb r0, [r0, #4] 504; CHECK-V7-LE-NEXT: and r0, r0, #1 505; CHECK-V7-LE-NEXT: bx lr 506; 507; CHECK-BE-LABEL: test_40_1_32: 508; CHECK-BE: @ %bb.0: 509; CHECK-BE-NEXT: ldrb r0, [r0] 510; CHECK-BE-NEXT: and r0, r0, #1 511; CHECK-BE-NEXT: mov pc, lr 512; 513; CHECK-V7-BE-LABEL: test_40_1_32: 514; CHECK-V7-BE: @ %bb.0: 515; CHECK-V7-BE-NEXT: ldrb r0, [r0] 516; CHECK-V7-BE-NEXT: and r0, r0, #1 517; CHECK-V7-BE-NEXT: bx lr 518 %a = load i40, ptr %y 519 %b = and i40 %a, u0x100000000 520 %cmp = icmp ne i40 %b, 0 521 ret i1 %cmp 522} 523 524define i1 @test_24_16_0(ptr %y) { 525; CHECK-LE-LABEL: test_24_16_0: 526; CHECK-LE: @ %bb.0: 527; CHECK-LE-NEXT: ldrh r0, [r0] 528; CHECK-LE-NEXT: cmp r0, #0 529; CHECK-LE-NEXT: movne r0, #1 530; CHECK-LE-NEXT: mov pc, lr 531; 532; CHECK-V7-LE-LABEL: test_24_16_0: 533; CHECK-V7-LE: @ %bb.0: 534; CHECK-V7-LE-NEXT: ldrh r0, [r0] 535; CHECK-V7-LE-NEXT: cmp r0, #0 536; CHECK-V7-LE-NEXT: movwne r0, #1 537; CHECK-V7-LE-NEXT: bx lr 538; 539; CHECK-BE-LABEL: test_24_16_0: 540; CHECK-BE: @ %bb.0: 541; CHECK-BE-NEXT: ldrh r0, [r0, #1] 542; CHECK-BE-NEXT: cmp r0, #0 543; CHECK-BE-NEXT: movne r0, #1 544; CHECK-BE-NEXT: mov pc, lr 545; 546; CHECK-V7-BE-LABEL: test_24_16_0: 547; CHECK-V7-BE: @ %bb.0: 548; CHECK-V7-BE-NEXT: ldrh r0, [r0, #1] 549; CHECK-V7-BE-NEXT: cmp r0, #0 550; CHECK-V7-BE-NEXT: movwne r0, #1 551; CHECK-V7-BE-NEXT: bx lr 552 %a = load i24, ptr %y 553 %b = and i24 %a, u0xffff 554 %cmp = icmp ne i24 %b, 0 555 ret i1 %cmp 556} 557 558define i1 @test_24_8_8(ptr %y) { 559; CHECK-LE-LABEL: test_24_8_8: 560; CHECK-LE: @ %bb.0: 561; CHECK-LE-NEXT: ldrb r0, [r0, #1] 562; CHECK-LE-NEXT: lsls r0, r0, #8 563; CHECK-LE-NEXT: movne r0, #1 564; CHECK-LE-NEXT: mov pc, lr 565; 566; CHECK-V7-LE-LABEL: test_24_8_8: 567; CHECK-V7-LE: @ %bb.0: 568; CHECK-V7-LE-NEXT: ldrb r0, [r0, #1] 569; CHECK-V7-LE-NEXT: lsls r0, r0, #8 570; CHECK-V7-LE-NEXT: movwne r0, #1 571; CHECK-V7-LE-NEXT: bx lr 572; 573; CHECK-BE-LABEL: test_24_8_8: 574; CHECK-BE: @ %bb.0: 575; CHECK-BE-NEXT: ldrb r0, [r0, #1] 576; CHECK-BE-NEXT: lsls r0, r0, #8 577; CHECK-BE-NEXT: movne r0, #1 578; CHECK-BE-NEXT: mov pc, lr 579; 580; CHECK-V7-BE-LABEL: test_24_8_8: 581; CHECK-V7-BE: @ %bb.0: 582; CHECK-V7-BE-NEXT: ldrb r0, [r0, #1] 583; CHECK-V7-BE-NEXT: lsls r0, r0, #8 584; CHECK-V7-BE-NEXT: movwne r0, #1 585; CHECK-V7-BE-NEXT: bx lr 586 %a = load i24, ptr %y 587 %b = and i24 %a, u0xff00 588 %cmp = icmp ne i24 %b, 0 589 ret i1 %cmp 590} 591 592define i1 @test_24_8_12(ptr %y) { 593; CHECK-LE-LABEL: test_24_8_12: 594; CHECK-LE: @ %bb.0: 595; CHECK-LE-NEXT: ldrb r1, [r0, #2] 596; CHECK-LE-NEXT: ldrh r0, [r0] 597; CHECK-LE-NEXT: orr r0, r0, r1, lsl #16 598; CHECK-LE-NEXT: ands r0, r0, #1044480 599; CHECK-LE-NEXT: movne r0, #1 600; CHECK-LE-NEXT: mov pc, lr 601; 602; CHECK-V7-LE-LABEL: test_24_8_12: 603; CHECK-V7-LE: @ %bb.0: 604; CHECK-V7-LE-NEXT: ldrb r1, [r0, #2] 605; CHECK-V7-LE-NEXT: ldrh r0, [r0] 606; CHECK-V7-LE-NEXT: orr r0, r0, r1, lsl #16 607; CHECK-V7-LE-NEXT: ands r0, r0, #1044480 608; CHECK-V7-LE-NEXT: movwne r0, #1 609; CHECK-V7-LE-NEXT: bx lr 610; 611; CHECK-BE-LABEL: test_24_8_12: 612; CHECK-BE: @ %bb.0: 613; CHECK-BE-NEXT: ldrh r0, [r0] 614; CHECK-BE-NEXT: mov r1, #1044480 615; CHECK-BE-NEXT: ands r0, r1, r0, lsl #8 616; CHECK-BE-NEXT: movne r0, #1 617; CHECK-BE-NEXT: mov pc, lr 618; 619; CHECK-V7-BE-LABEL: test_24_8_12: 620; CHECK-V7-BE: @ %bb.0: 621; CHECK-V7-BE-NEXT: ldrh r0, [r0] 622; CHECK-V7-BE-NEXT: mov r1, #1044480 623; CHECK-V7-BE-NEXT: ands r0, r1, r0, lsl #8 624; CHECK-V7-BE-NEXT: movwne r0, #1 625; CHECK-V7-BE-NEXT: bx lr 626 %a = load i24, ptr %y 627 %b = and i24 %a, u0xff000 628 %cmp = icmp ne i24 %b, 0 629 ret i1 %cmp 630} 631 632define i1 @test_24_8_16(ptr %y) { 633; CHECK-LE-LABEL: test_24_8_16: 634; CHECK-LE: @ %bb.0: 635; CHECK-LE-NEXT: ldrb r0, [r0, #2] 636; CHECK-LE-NEXT: lsls r0, r0, #16 637; CHECK-LE-NEXT: movne r0, #1 638; CHECK-LE-NEXT: mov pc, lr 639; 640; CHECK-V7-LE-LABEL: test_24_8_16: 641; CHECK-V7-LE: @ %bb.0: 642; CHECK-V7-LE-NEXT: ldrb r0, [r0, #2] 643; CHECK-V7-LE-NEXT: lsls r0, r0, #16 644; CHECK-V7-LE-NEXT: movwne r0, #1 645; CHECK-V7-LE-NEXT: bx lr 646; 647; CHECK-BE-LABEL: test_24_8_16: 648; CHECK-BE: @ %bb.0: 649; CHECK-BE-NEXT: ldrb r0, [r0] 650; CHECK-BE-NEXT: lsls r0, r0, #16 651; CHECK-BE-NEXT: movne r0, #1 652; CHECK-BE-NEXT: mov pc, lr 653; 654; CHECK-V7-BE-LABEL: test_24_8_16: 655; CHECK-V7-BE: @ %bb.0: 656; CHECK-V7-BE-NEXT: ldrb r0, [r0] 657; CHECK-V7-BE-NEXT: lsls r0, r0, #16 658; CHECK-V7-BE-NEXT: movwne r0, #1 659; CHECK-V7-BE-NEXT: bx lr 660 %a = load i24, ptr %y 661 %b = and i24 %a, u0xff0000 662 %cmp = icmp ne i24 %b, 0 663 ret i1 %cmp 664} 665