xref: /llvm-project/llvm/test/CodeGen/ARM/long_shift.ll (revision 79937dfc5b79f1337c36a178bdb38f7d06311983)
1; RUN: llc < %s -march=arm | FileCheck %s
2
3define i64 @f0(i64 %A, i64 %B) {
4; CHECK: f0
5; CHECK:      movs    r3, r3, lsr #1
6; CHECK-NEXT: mov     r2, r2, rrx
7; CHECK-NEXT: subs    r0, r0, r2
8; CHECK-NEXT: sbc     r1, r1, r3
9	%tmp = bitcast i64 %A to i64
10	%tmp2 = lshr i64 %B, 1
11	%tmp3 = sub i64 %tmp, %tmp2
12	ret i64 %tmp3
13}
14
15define i32 @f1(i64 %x, i64 %y) {
16; CHECK: f1
17; CHECK: mov r0, r0, lsl r2
18	%a = shl i64 %x, %y
19	%b = trunc i64 %a to i32
20	ret i32 %b
21}
22
23define i32 @f2(i64 %x, i64 %y) {
24; CHECK: f2
25; CHECK:      mov     r0, r0, lsr r2
26; CHECK-NEXT: rsb     r3, r2, #32
27; CHECK-NEXT: subs    r2, r2, #32
28; CHECK-NEXT: orr     r0, r0, r1, lsl r3
29; CHECK-NEXT: movge   r0, r1, asr r2
30	%a = ashr i64 %x, %y
31	%b = trunc i64 %a to i32
32	ret i32 %b
33}
34
35define i32 @f3(i64 %x, i64 %y) {
36; CHECK: f3
37; CHECK:      mov     r0, r0, lsr r2
38; CHECK-NEXT: rsb     r3, r2, #32
39; CHECK-NEXT: subs    r2, r2, #32
40; CHECK-NEXT: orr     r0, r0, r1, lsl r3
41; CHECK-NEXT: movge   r0, r1, lsr r2
42	%a = lshr i64 %x, %y
43	%b = trunc i64 %a to i32
44	ret i32 %b
45}
46