[ARM] Remove more unused check prefixes, NFC

[ARM] Favour PL/MI over GE/LT when possible

The arm condition codes for GE is N==V (and for LT is N!=V). If the source of
flags cannot set V (overflow), such as a cmp against #0, then we can use the

[ARM] Favour PL/MI over GE/LT when possible

The arm condition codes for GE is N==V (and for LT is N!=V). If the source of
flags cannot set V (overflow), such as a cmp against #0, then we can use the
simpler PL and MI conditions that only check N. As these PL/MI conditions are
simpler than GE/LT, other passes like the peephole optimiser can have a better
time optimising away the redundant CMPs.

The exception is the VSEL instruction, which cannot take the PL code, so there
the transform favours GE.

Differential Revision: https://reviews.llvm.org/D64160

llvm-svn: 365117

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[ARM] Added testing for D64160. NFC

Adds some extra vsel testing and regenerates long shift and saturation bitop
tests.

llvm-svn: 365116

[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).

The benchmarking summarized in
http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed
this is beneficial for a wide

[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).

The benchmarking summarized in
http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed
this is beneficial for a wide range of cores.

As is to be expected, quite a few small adaptations are needed to the
regressions tests, as the difference in scheduling results in:
- Quite a few small instruction schedule differences.
- A few changes in register allocation decisions caused by different
instruction schedules.
- A few changes in IfConversion decisions, due to a difference in
instruction schedule and/or the estimated cost of a branch mispredict.

llvm-svn: 306514

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ARM big endian function argument passing

llvm-svn: 208316

ARM: fixup more tests to specify the target more explicitly

This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default. This breaks

ARM: fixup more tests to specify the target more explicitly

This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default. This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.

Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.

llvm-svn: 205541

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Revert "Tests: Be less dependent on a specific schedule/regalloc"

This reverts r192454

Apparently FileCheck isn't as smart as I though and does not enforce a
topological order between variable defs

Revert "Tests: Be less dependent on a specific schedule/regalloc"

This reverts r192454

Apparently FileCheck isn't as smart as I though and does not enforce a
topological order between variable defs+uses.

llvm-svn: 192472

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Tests: Be less dependent on a specific schedule/regalloc

llvm-svn: 192454

Tests: Use CHECK-LABEL where possible

llvm-svn: 192403

- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruct

- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.

llvm-svn: 146542

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Cmp peephole optimization isn't always safe for signed arithmetics.

int tries = INT_MAX;
while (tries > 0) {
tries--;
}

The check should be:
subs r4, #1
cmp r4, #0

Cmp peephole optimization isn't always safe for signed arithmetics.

int tries = INT_MAX;
while (tries > 0) {
tries--;
}

The check should be:
subs r4, #1
cmp r4, #0
bgt LBB0_1

The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.

rdar://9172742

llvm-svn: 128179

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Properly pseudo-ize MOVCCr and MOVCCs.

llvm-svn: 127434

When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:

(1) subs ...
(2) sub r6, r5, r4
(3) movge ..

When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:

(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950

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More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the
peephole optimizer is disabled. That's not good at all.

llvm-svn: 117905

Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534

Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.

llvm-svn: 116512

Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "ls

Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.

llvm-svn: 114221

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Update test to match output of optimize compares for ARM.

llvm-svn: 110765

Teach EmitLiveInCopies to omit copies for unused virtual registers,
and to clean up unused incoming physregs from the live-in list.

llvm-svn: 106805

Run codegen dce pass for all targets at all optimization levels. Previously it's
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of

Run codegen dce pass for all targets at all optimization levels. Previously it's
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493

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Update test to be more explicit about what instruction sequences are expected for each operation.

llvm-svn: 85689

Expand 64-bit logical shift right inline

llvm-svn: 85687

Expand 64-bit arithmetic shift right inline

llvm-svn: 85685

Expand 64 bit left shift inline rather than using the libcall. For now, this
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675

Add missing colons for FileCheck.

llvm-svn: 85674