1# RUN: llc -mcpu=cortex-m33 -run-pass=arm-pseudo %s -o - | FileCheck %s 2--- | 3 target datalayout = "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4 target triple = "thumbebv8m.main-arm-none-eabi" 5 6 ; Function Attrs: cmse_nonsecure_entry nounwind 7 define hidden arm_aapcs_vfpcc void @secure_foo(ptr %fptr) local_unnamed_addr #0 { 8 entry: 9 %0 = ptrtoint ptr %fptr to i32 10 %and = and i32 %0, -2 11 %1 = inttoptr i32 %and to ptr 12 call arm_aapcs_vfpcc void %1(double 0.000000e+00, double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00, double 5.000000e+00, double 6.000000e+00, double 7.000000e+00) #2 13 ret void 14 } 15 16 ; Function Attrs: nounwind 17 declare void @llvm.stackprotector(ptr, ptr) #1 18 19 attributes #0 = { "cmse_nonsecure_entry" nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+8msecext,+armv8-m.main,-d32,-fp64,+fp-armv8,+hwdiv,+thumb-mode,-crypto,-fullfp16,-neon" "unsafe-fp-math"="false" "use-soft-float"="false" } 20 attributes #1 = { nounwind } 21 attributes #2 = { "cmse_nonsecure_call" nounwind } 22 23 !llvm.module.flags = !{!0, !1, !2, !3} 24 25 !0 = !{i32 1, !"wchar_size", i32 4} 26 !1 = !{i32 1, !"static_rwdata", i32 1} 27 !2 = !{i32 1, !"enumsize_buildattr", i32 2} 28 !3 = !{i32 1, !"armlib_unavailable", i32 0} 29 30... 31--- 32name: secure_foo 33alignment: 2 34tracksRegLiveness: true 35liveins: 36 - { reg: '$r0' } 37frameInfo: 38 stackSize: 8 39 maxAlignment: 4 40 adjustsStack: true 41 hasCalls: true 42 maxCallFrameSize: 0 43stack: 44 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, 45 callee-saved-register: '$lr' } 46 - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default, 47 callee-saved-register: '$r7' } 48constants: 49 - id: 0 50 value: 'double 0.000000e+00' 51 alignment: 8 52 - id: 1 53 value: 'double 1.000000e+00' 54 alignment: 8 55 - id: 2 56 value: 'double 2.000000e+00' 57 alignment: 8 58 - id: 3 59 value: 'double 3.000000e+00' 60 alignment: 8 61 - id: 4 62 value: 'double 4.000000e+00' 63 alignment: 8 64 - id: 5 65 value: 'double 5.000000e+00' 66 alignment: 8 67 - id: 6 68 value: 'double 6.000000e+00' 69 alignment: 8 70 - id: 7 71 value: 'double 7.000000e+00' 72 alignment: 8 73body: | 74 bb.0.entry: 75 liveins: $r0, $r7, $lr 76 77 $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr 78 frame-setup CFI_INSTRUCTION def_cfa_offset 8 79 frame-setup CFI_INSTRUCTION offset $lr, -4 80 frame-setup CFI_INSTRUCTION offset $r7, -8 81 renamable $d0 = VLDRD %const.0, 0, 14, $noreg :: (load (s64) from constant-pool) 82 renamable $d1 = VLDRD %const.1, 0, 14, $noreg :: (load (s64) from constant-pool) 83 renamable $d2 = VLDRD %const.2, 0, 14, $noreg :: (load (s64) from constant-pool) 84 renamable $d3 = VLDRD %const.3, 0, 14, $noreg :: (load (s64) from constant-pool) 85 renamable $d4 = VLDRD %const.4, 0, 14, $noreg :: (load (s64) from constant-pool) 86 renamable $d5 = VLDRD %const.5, 0, 14, $noreg :: (load (s64) from constant-pool) 87 renamable $d6 = VLDRD %const.6, 0, 14, $noreg :: (load (s64) from constant-pool) 88 renamable $d7 = VLDRD %const.7, 0, 14, $noreg :: (load (s64) from constant-pool) 89 renamable $r0 = t2BICri killed renamable $r0, 1, 14, $noreg, $noreg 90 tBLXNS_CALL killed renamable $r0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $d3, implicit $d4, implicit $d5, implicit $d6, implicit $d7, implicit-def $sp 91 $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr 92 tBXNS_RET 93 94... 95 96# CHECK: VLSTM 97# CHECK-DAG: $s12 = VLDRS $sp, 12, 14 /* CC::al */, $noreg 98# CHECK-DAG: $s13 = VLDRS $sp, 13, 14 /* CC::al */, $noreg 99# CHECK-DAG: $s14 = VLDRS $sp, 14, 14 /* CC::al */, $noreg 100# CHECK-DAG: $s15 = VLDRS $sp, 15, 14 /* CC::al */, $noreg 101# CHECK: tBLXNSr 102