1;; Check that epilogues aren't tail merged. 2 3;; Check that this produces the expected assembly output 4; RUN: llc -mtriple=thumbv7-windows -o - %s -verify-machineinstrs | FileCheck %s 5;; Also try to write an object file, which verifies that the SEH opcodes 6;; match the actual prologue/epilogue length. 7; RUN: llc -mtriple=thumbv7-windows -filetype=obj -o %t.obj %s -verify-machineinstrs 8 9; CHECK-LABEL: d: 10; CHECK: .seh_proc d 11 12; CHECK: push.w {r11, lr} 13; CHECK-NEXT: .seh_save_regs_w {r11, lr} 14; CHECK-NEXT: .seh_endprologue 15 16; CHECK: .seh_startepilogue 17; CHECK-NEXT: pop.w {r11, lr} 18; CHECK-NEXT: .seh_save_regs_w {r11, lr} 19; CHECK-NEXT: b.w b 20; CHECK-NEXT: .seh_nop_w 21; CHECK-NEXT: .seh_endepilogue 22 23; CHECK: .seh_startepilogue 24; CHECK-NEXT: pop.w {r11, lr} 25; CHECK-NEXT: .seh_save_regs_w {r11, lr} 26; CHECK-NEXT: b.w c 27; CHECK-NEXT: .seh_nop_w 28; CHECK-NEXT: .seh_endepilogue 29; CHECK-NEXT: .seh_endproc 30 31@a = global i32 0, align 4 32 33define arm_aapcs_vfpcc void @d() optsize uwtable "frame-pointer"="none" { 34entry: 35 %0 = load i32, ptr @a, align 4 36 switch i32 %0, label %if.then1 [ 37 i32 10, label %if.then 38 i32 0, label %if.end2 39 ] 40 41if.then: 42 tail call arm_aapcs_vfpcc void @b() 43 br label %return 44 45if.then1: 46 tail call arm_aapcs_vfpcc void @b() 47 br label %if.end2 48 49if.end2: 50 tail call arm_aapcs_vfpcc void @c() 51 br label %return 52 53return: 54 ret void 55} 56 57declare arm_aapcs_vfpcc void @b(...) 58 59declare arm_aapcs_vfpcc void @c(...) 60