xref: /llvm-project/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-shifts.mir (revision 7efabe5c7de46fe190638741c6ee81ae13255e38) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3--- |
4  define void @test_ashr_rr() { ret void }
5
6  define void @test_shl_ri() { ret void }
7  define void @test_shl_ri_bad_imm() { ret void }
8...
9---
10name:            test_ashr_rr
11legalized:       true
12regBankSelected: true
13selected:        false
14registers:
15  - { id: 0, class: gprb }
16  - { id: 1, class: gprb }
17  - { id: 2, class: gprb }
18body:             |
19  bb.0:
20    liveins: $r0, $r1
21
22    ; CHECK-LABEL: name: test_ashr_rr
23    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
24    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
25    ; CHECK: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
26    ; CHECK: $r0 = COPY [[t2ASRrr]]
27    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
28    %0(s32) = COPY $r0
29
30    %1(s32) = COPY $r1
31
32    %2(s32) = G_ASHR %0, %1
33
34    $r0 = COPY %2(s32)
35
36    BX_RET 14, $noreg, implicit $r0
37...
38---
39name:            test_shl_ri
40legalized:       true
41regBankSelected: true
42selected:        false
43registers:
44  - { id: 0, class: gprb }
45  - { id: 1, class: gprb }
46  - { id: 2, class: gprb }
47body:             |
48  bb.0:
49    liveins: $r0
50
51    ; CHECK-LABEL: name: test_shl_ri
52    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
53    ; CHECK: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 31, 14 /* CC::al */, $noreg, $noreg
54    ; CHECK: $r0 = COPY [[t2LSLri]]
55    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
56    %0(s32) = COPY $r0
57
58    %1(s32) = G_CONSTANT i32 31
59    %2(s32) = G_SHL %0, %1
60
61    $r0 = COPY %2(s32)
62
63    BX_RET 14, $noreg, implicit $r0
64...
65---
66name:            test_shl_ri_bad_imm
67legalized:       true
68regBankSelected: true
69selected:        false
70registers:
71  - { id: 0, class: gprb }
72  - { id: 1, class: gprb }
73  - { id: 2, class: gprb }
74body:             |
75  bb.0:
76    liveins: $r0
77
78    ; CHECK-LABEL: name: test_shl_ri_bad_imm
79    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
80    ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 32, 14 /* CC::al */, $noreg, $noreg
81    ; CHECK: [[t2LSLrr:%[0-9]+]]:rgpr = t2LSLrr [[COPY]], [[t2MOVi]], 14 /* CC::al */, $noreg, $noreg
82    ; CHECK: $r0 = COPY [[t2LSLrr]]
83    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
84    %0(s32) = COPY $r0
85
86    %1(s32) = G_CONSTANT i32 32
87
88    %2(s32) = G_SHL %0, %1
89
90    $r0 = COPY %2(s32)
91
92    BX_RET 14, $noreg, implicit $r0
93...
94