xref: /llvm-project/llvm/test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll (revision 5615fa0a87c8ff43756bb885b8473add2165f300)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
3
4define <3 x i64> @shuffle(i1 %dec1, i1 %dec0, <3 x i64> %b) {
5; CHECK-LABEL: shuffle:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    tst r1, #1
8; CHECK-NEXT:    moveq r1, #0
9; CHECK-NEXT:    vmoveq d16, r1, r1
10; CHECK-NEXT:    vldrne d16, [sp]
11; CHECK-NEXT:    tst r2, #1
12; CHECK-NEXT:    moveq r1, #0
13; CHECK-NEXT:    vmoveq d18, r1, r1
14; CHECK-NEXT:    vldrne d18, [sp, #8]
15; CHECK-NEXT:    vorr d17, d18, d18
16; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128]
17; CHECK-NEXT:    bx lr
18entry:
19  %.sink = select i1 %dec1, <3 x i64> %b, <3 x i64> zeroinitializer
20  %.sink15 = select i1 %dec0, <3 x i64> %b, <3 x i64> zeroinitializer
21  %vecinit7 = shufflevector <3 x i64> %.sink, <3 x i64> %.sink15, <3 x i32> <i32 0, i32 4, i32 undef>
22  ret <3 x i64> %vecinit7
23}
24