1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s 3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s 4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s 5 6; =================================================================================== 7; V_XOR3_B32 8; =================================================================================== 9 10define amdgpu_ps float @xor3(i32 %a, i32 %b, i32 %c) { 11; GFX9-LABEL: xor3: 12; GFX9: ; %bb.0: 13; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 14; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 15; GFX9-NEXT: ; return to shader part epilog 16; 17; GFX10-LABEL: xor3: 18; GFX10: ; %bb.0: 19; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2 20; GFX10-NEXT: ; return to shader part epilog 21 %x = xor i32 %a, %b 22 %result = xor i32 %x, %c 23 %bc = bitcast i32 %result to float 24 ret float %bc 25} 26 27define amdgpu_ps float @xor3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) { 28; GFX9-LABEL: xor3_vgpr_b: 29; GFX9: ; %bb.0: 30; GFX9-NEXT: s_xor_b32 s0, s3, s2 31; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 32; GFX9-NEXT: ; return to shader part epilog 33; 34; GFX10-LABEL: xor3_vgpr_b: 35; GFX10: ; %bb.0: 36; GFX10-NEXT: v_xor3_b32 v0, s3, s2, v0 37; GFX10-NEXT: ; return to shader part epilog 38 %x = xor i32 %a, %b 39 %result = xor i32 %x, %c 40 %bc = bitcast i32 %result to float 41 ret float %bc 42} 43 44define amdgpu_ps float @xor3_vgpr_all2(i32 %a, i32 %b, i32 %c) { 45; GFX9-LABEL: xor3_vgpr_all2: 46; GFX9: ; %bb.0: 47; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2 48; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 49; GFX9-NEXT: ; return to shader part epilog 50; 51; GFX10-LABEL: xor3_vgpr_all2: 52; GFX10: ; %bb.0: 53; GFX10-NEXT: v_xor3_b32 v0, v1, v2, v0 54; GFX10-NEXT: ; return to shader part epilog 55 %x = xor i32 %b, %c 56 %result = xor i32 %a, %x 57 %bc = bitcast i32 %result to float 58 ret float %bc 59} 60 61define amdgpu_ps float @xor3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) { 62; GFX9-LABEL: xor3_vgpr_bc: 63; GFX9: ; %bb.0: 64; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 65; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 66; GFX9-NEXT: ; return to shader part epilog 67; 68; GFX10-LABEL: xor3_vgpr_bc: 69; GFX10: ; %bb.0: 70; GFX10-NEXT: v_xor3_b32 v0, s2, v0, v1 71; GFX10-NEXT: ; return to shader part epilog 72 %x = xor i32 %a, %b 73 %result = xor i32 %x, %c 74 %bc = bitcast i32 %result to float 75 ret float %bc 76} 77 78define amdgpu_ps float @xor3_vgpr_const(i32 %a, i32 %b) { 79; GFX9-LABEL: xor3_vgpr_const: 80; GFX9: ; %bb.0: 81; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 82; GFX9-NEXT: v_xor_b32_e32 v0, 16, v0 83; GFX9-NEXT: ; return to shader part epilog 84; 85; GFX10-LABEL: xor3_vgpr_const: 86; GFX10: ; %bb.0: 87; GFX10-NEXT: v_xor3_b32 v0, v0, v1, 16 88; GFX10-NEXT: ; return to shader part epilog 89 %x = xor i32 %a, %b 90 %result = xor i32 %x, 16 91 %bc = bitcast i32 %result to float 92 ret float %bc 93} 94 95define amdgpu_ps <2 x float> @xor3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) { 96; GFX9-LABEL: xor3_multiuse_outer: 97; GFX9: ; %bb.0: 98; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 99; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 100; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3 101; GFX9-NEXT: ; return to shader part epilog 102; 103; GFX10-LABEL: xor3_multiuse_outer: 104; GFX10: ; %bb.0: 105; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2 106; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3 107; GFX10-NEXT: ; return to shader part epilog 108 %inner = xor i32 %a, %b 109 %outer = xor i32 %inner, %c 110 %x1 = mul i32 %outer, %x 111 %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0 112 %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1 113 %bc = bitcast <2 x i32> %r0 to <2 x float> 114 ret <2 x float> %bc 115} 116 117define amdgpu_ps <2 x float> @xor3_multiuse_inner(i32 %a, i32 %b, i32 %c) { 118; GFX9-LABEL: xor3_multiuse_inner: 119; GFX9: ; %bb.0: 120; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 121; GFX9-NEXT: v_xor_b32_e32 v1, v0, v2 122; GFX9-NEXT: ; return to shader part epilog 123; 124; GFX10-LABEL: xor3_multiuse_inner: 125; GFX10: ; %bb.0: 126; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1 127; GFX10-NEXT: v_xor_b32_e32 v1, v0, v2 128; GFX10-NEXT: ; return to shader part epilog 129 %inner = xor i32 %a, %b 130 %outer = xor i32 %inner, %c 131 %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0 132 %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1 133 %bc = bitcast <2 x i32> %r0 to <2 x float> 134 ret <2 x float> %bc 135} 136 137; A case where uniform values end up in VGPRs -- we could use v_xor3_b32 here, 138; but we don't. 139define amdgpu_ps float @xor3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) { 140; GFX9-LABEL: xor3_uniform_vgpr: 141; GFX9: ; %bb.0: 142; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0 143; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0 144; GFX9-NEXT: v_mov_b32_e32 v2, 0x40400000 145; GFX9-NEXT: v_add_f32_e32 v2, s4, v2 146; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 147; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 148; GFX9-NEXT: ; return to shader part epilog 149; 150; GFX10-LABEL: xor3_uniform_vgpr: 151; GFX10: ; %bb.0: 152; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0 153; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0 154; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4 155; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1 156; GFX10-NEXT: v_xor_b32_e32 v0, v0, v2 157; GFX10-NEXT: ; return to shader part epilog 158 %a1 = fadd float %a, 1.0 159 %b2 = fadd float %b, 2.0 160 %c3 = fadd float %c, 3.0 161 %bc.a = bitcast float %a1 to i32 162 %bc.b = bitcast float %b2 to i32 163 %bc.c = bitcast float %c3 to i32 164 %x = xor i32 %bc.a, %bc.b 165 %result = xor i32 %x, %bc.c 166 %bc = bitcast i32 %result to float 167 ret float %bc 168} 169