1; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s 2; RUN: llc -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s 3; RUN: llc -mtriple=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s 4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s 5; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-DL %s 6 7; GCN-LABEL: {{^}}scalar_xnor_i32_one_use 8; GCN: s_xnor_b32 9define amdgpu_kernel void @scalar_xnor_i32_one_use( 10 ptr addrspace(1) %r0, i32 %a, i32 %b) { 11entry: 12 %xor = xor i32 %a, %b 13 %r0.val = xor i32 %xor, -1 14 store i32 %r0.val, ptr addrspace(1) %r0 15 ret void 16} 17 18; GCN-LABEL: {{^}}scalar_xnor_i32_mul_use 19; GCN-NOT: s_xnor_b32 20; GCN: s_xor_b32 21; GCN: s_not_b32 22; GCN: s_add_i32 23define amdgpu_kernel void @scalar_xnor_i32_mul_use( 24 ptr addrspace(1) %r0, ptr addrspace(1) %r1, i32 %a, i32 %b) { 25entry: 26 %xor = xor i32 %a, %b 27 %r0.val = xor i32 %xor, -1 28 %r1.val = add i32 %xor, %a 29 store i32 %r0.val, ptr addrspace(1) %r0 30 store i32 %r1.val, ptr addrspace(1) %r1 31 ret void 32} 33 34; GCN-LABEL: {{^}}scalar_xnor_i64_one_use 35; GCN: s_xnor_b64 36define amdgpu_kernel void @scalar_xnor_i64_one_use( 37 ptr addrspace(1) %r0, i64 %a, i64 %b) { 38entry: 39 %xor = xor i64 %a, %b 40 %r0.val = xor i64 %xor, -1 41 store i64 %r0.val, ptr addrspace(1) %r0 42 ret void 43} 44 45; GCN-LABEL: {{^}}scalar_xnor_i64_mul_use 46; GCN-NOT: s_xnor_b64 47; GCN: s_xor_b64 48; GCN: s_not_b64 49; GCN: s_add_u32 50; GCN: s_addc_u32 51define amdgpu_kernel void @scalar_xnor_i64_mul_use( 52 ptr addrspace(1) %r0, ptr addrspace(1) %r1, i64 %a, i64 %b) { 53entry: 54 %xor = xor i64 %a, %b 55 %r0.val = xor i64 %xor, -1 56 %r1.val = add i64 %xor, %a 57 store i64 %r0.val, ptr addrspace(1) %r0 58 store i64 %r1.val, ptr addrspace(1) %r1 59 ret void 60} 61 62; GCN-LABEL: {{^}}vector_xnor_i32_one_use 63; GCN-NOT: s_xnor_b32 64; GCN: v_xor_b32 65; GCN: v_not_b32 66; GCN-DL: v_xnor_b32 67define i32 @vector_xnor_i32_one_use(i32 %a, i32 %b) { 68entry: 69 %xor = xor i32 %a, %b 70 %r = xor i32 %xor, -1 71 ret i32 %r 72} 73 74; GCN-LABEL: {{^}}vector_xnor_i64_one_use 75; GCN-NOT: s_xnor_b64 76; GCN: v_xor_b32 77; GCN: v_xor_b32 78; GCN: v_not_b32 79; GCN: v_not_b32 80; GCN-DL: v_xnor_b32 81; GCN-DL: v_xnor_b32 82define i64 @vector_xnor_i64_one_use(i64 %a, i64 %b) { 83entry: 84 %xor = xor i64 %a, %b 85 %r = xor i64 %xor, -1 86 ret i64 %r 87} 88 89; GCN-LABEL: {{^}}xnor_s_v_i32_one_use 90; GCN-NOT: s_xnor_b32 91; GCN: s_not_b32 92; GCN: v_xor_b32 93define amdgpu_kernel void @xnor_s_v_i32_one_use(ptr addrspace(1) %out, i32 %s) { 94 %v = call i32 @llvm.amdgcn.workitem.id.x() #1 95 %xor = xor i32 %s, %v 96 %d = xor i32 %xor, -1 97 store i32 %d, ptr addrspace(1) %out 98 ret void 99} 100 101; GCN-LABEL: {{^}}xnor_v_s_i32_one_use 102; GCN-NOT: s_xnor_b32 103; GCN: s_not_b32 104; GCN: v_xor_b32 105define amdgpu_kernel void @xnor_v_s_i32_one_use(ptr addrspace(1) %out, i32 %s) { 106 %v = call i32 @llvm.amdgcn.workitem.id.x() #1 107 %xor = xor i32 %v, %s 108 %d = xor i32 %xor, -1 109 store i32 %d, ptr addrspace(1) %out 110 ret void 111} 112 113; GCN-LABEL: {{^}}xnor_i64_s_v_one_use 114; GCN-NOT: s_xnor_b64 115; GCN: s_not_b64 116; GCN: v_xor_b32_e32 117; GCN-DL: v_xnor_b32 118; GCN-DL: v_xnor_b32 119define amdgpu_kernel void @xnor_i64_s_v_one_use( 120 ptr addrspace(1) %r0, i64 %a) { 121entry: 122 %b32 = call i32 @llvm.amdgcn.workitem.id.x() #1 123 %b64 = zext i32 %b32 to i64 124 %b = shl i64 %b64, 29 125 %xor = xor i64 %a, %b 126 %r0.val = xor i64 %xor, -1 127 store i64 %r0.val, ptr addrspace(1) %r0 128 ret void 129} 130 131; GCN-LABEL: {{^}}xnor_i64_v_s_one_use 132; GCN-NOT: s_xnor_b64 133; GCN: s_not_b64 134; GCN: v_xor_b32_e32 135; GCN-DL: v_xnor_b32 136; GCN-DL: v_xnor_b32 137define amdgpu_kernel void @xnor_i64_v_s_one_use( 138 ptr addrspace(1) %r0, i64 %a) { 139entry: 140 %b32 = call i32 @llvm.amdgcn.workitem.id.x() #1 141 %b64 = zext i32 %b32 to i64 142 %b = shl i64 %b64, 29 143 %xor = xor i64 %b, %a 144 %r0.val = xor i64 %xor, -1 145 store i64 %r0.val, ptr addrspace(1) %r0 146 ret void 147} 148 149; GCN-LABEL: {{^}}vector_xor_na_b_i32_one_use 150; GCN-NOT: s_xnor_b32 151; GCN: v_xor_b32 152; GCN: v_not_b32 153; GCN-DL: v_xnor_b32 154define i32 @vector_xor_na_b_i32_one_use(i32 %a, i32 %b) { 155entry: 156 %na = xor i32 %a, -1 157 %r = xor i32 %na, %b 158 ret i32 %r 159} 160 161; GCN-LABEL: {{^}}vector_xor_a_nb_i32_one_use 162; GCN-NOT: s_xnor_b32 163; GCN: v_xor_b32 164; GCN: v_not_b32 165; GCN-DL: v_xnor_b32 166define i32 @vector_xor_a_nb_i32_one_use(i32 %a, i32 %b) { 167entry: 168 %nb = xor i32 %b, -1 169 %r = xor i32 %a, %nb 170 ret i32 %r 171} 172 173; GCN-LABEL: {{^}}scalar_xor_a_nb_i64_one_use 174; GCN: s_xnor_b64 175define amdgpu_kernel void @scalar_xor_a_nb_i64_one_use( 176 ptr addrspace(1) %r0, i64 %a, i64 %b) { 177entry: 178 %nb = xor i64 %b, -1 179 %r0.val = xor i64 %a, %nb 180 store i64 %r0.val, ptr addrspace(1) %r0 181 ret void 182} 183 184; GCN-LABEL: {{^}}scalar_xor_na_b_i64_one_use 185; GCN: s_xnor_b64 186define amdgpu_kernel void @scalar_xor_na_b_i64_one_use( 187 ptr addrspace(1) %r0, i64 %a, i64 %b) { 188entry: 189 %na = xor i64 %a, -1 190 %r0.val = xor i64 %na, %b 191 store i64 %r0.val, ptr addrspace(1) %r0 192 ret void 193} 194 195; Function Attrs: nounwind readnone 196declare i32 @llvm.amdgcn.workitem.id.x() #0 197