xref: /llvm-project/llvm/test/CodeGen/AMDGPU/wqm-terminators.mir (revision e7900e695e7dfb36be8651d914a31f42a5d6c634)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
2# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-wqm -o -  %s | FileCheck %s
3
4--- |
5  define amdgpu_ps void @exit_to_exact() {
6    ret void
7  }
8...
9---
10
11---
12name: exit_to_exact
13tracksRegLiveness: true
14registers:
15  - { id: 0, class: sgpr_32, preferred-register: '' }
16  - { id: 1, class: vreg_64, preferred-register: '' }
17  - { id: 2, class: sgpr_256, preferred-register: '' }
18  - { id: 3, class: sgpr_128, preferred-register: '' }
19  - { id: 4, class: vreg_96, preferred-register: '' }
20  - { id: 5, class: vreg_64, preferred-register: '' }
21  - { id: 6, class: vgpr_32, preferred-register: '' }
22liveins:
23  - { reg: '$sgpr0', virtual-reg: '%0' }
24body: |
25  ; CHECK-LABEL: name: exit_to_exact
26  ; CHECK: bb.0:
27  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
28  ; CHECK-NEXT:   liveins: $sgpr0, $vgpr0_vgpr1
29  ; CHECK-NEXT: {{  $}}
30  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $exec_lo
31  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
32  ; CHECK-NEXT:   $exec_lo = S_WQM_B32 $exec_lo, implicit-def $scc
33  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
34  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
35  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
36  ; CHECK-NEXT:   S_CMP_EQ_U32 [[COPY1]], 0, implicit-def $scc
37  ; CHECK-NEXT:   undef [[V_MUL_F32_e64_:%[0-9]+]].sub0:vreg_64 = V_MUL_F32_e64 0, [[COPY2]].sub0, 0, [[COPY2]].sub1, 0, 0, implicit $mode, implicit $exec
38  ; CHECK-NEXT:   [[V_MUL_F32_e64_:%[0-9]+]].sub1:vreg_64 = V_MUL_F32_e64 0, [[COPY2]].sub0, 0, [[COPY2]].sub1, 0, 0, implicit $mode, implicit $exec
39  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
40  ; CHECK-NEXT:   $exec_lo = S_AND_B32 $exec_lo, [[COPY]], implicit-def $scc
41  ; CHECK-NEXT:   $scc = COPY [[COPY3]]
42  ; CHECK-NEXT:   [[IMAGE_SAMPLE_V3_V2_gfx10_:%[0-9]+]]:vreg_96 = IMAGE_SAMPLE_V3_V2_gfx10 [[V_MUL_F32_e64_]], [[DEF]], [[DEF1]], 7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)
43  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
44  ; CHECK-NEXT:   S_BRANCH %bb.1
45  ; CHECK-NEXT: {{  $}}
46  ; CHECK-NEXT: bb.1:
47  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
48  ; CHECK-NEXT: {{  $}}
49  ; CHECK-NEXT: bb.2:
50  ; CHECK-NEXT:   [[V_SUB_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SUB_F32_e64 0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub0, 0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub1, 0, 0, implicit $mode, implicit $exec
51  ; CHECK-NEXT:   BUFFER_STORE_DWORD_OFFSET_exact [[V_SUB_F32_e64_]], [[DEF1]], [[COPY1]], 4, 0, 0, implicit $exec
52  ; CHECK-NEXT:   EXP 0, [[V_SUB_F32_e64_]], [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub1, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub2, 0, 0, 0, implicit $exec
53  ; CHECK-NEXT:   S_ENDPGM 0
54  bb.0:
55    liveins: $sgpr0, $vgpr0_vgpr1
56
57    %0 = COPY $sgpr0
58    %1 = COPY $vgpr0_vgpr1
59    %2 = IMPLICIT_DEF
60    %3 = IMPLICIT_DEF
61
62    S_CMP_EQ_U32 %0, 0, implicit-def $scc
63    undef %5.sub0 = V_MUL_F32_e64 0, %1.sub0, 0, %1.sub1, 0, 0, implicit $mode, implicit $exec
64    %5.sub1 = V_MUL_F32_e64 0, %1.sub0, 0, %1.sub1, 0, 0, implicit $mode, implicit $exec
65    %4 = IMAGE_SAMPLE_V3_V2_gfx10 %5, %2, %3, 7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)
66    S_CBRANCH_SCC1 %bb.2, implicit killed $scc
67    S_BRANCH %bb.1
68
69  bb.1:
70
71  bb.2:
72    %6 = nofpexcept V_SUB_F32_e64 0, %4.sub0, 0, %4.sub1, 0, 0, implicit $mode, implicit $exec
73    BUFFER_STORE_DWORD_OFFSET_exact %6, %3, %0, 4, 0, 0, implicit $exec
74    EXP 0, %6, %4.sub0, %4.sub1, %4.sub2, 0, 0, 0, implicit $exec
75    S_ENDPGM 0
76
77...
78