1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK %s 3 4; Test that s_wqm is executed before lds.param.load. 5define amdgpu_ps <3 x float> @test_param_load(i32 inreg %attr, <3 x float> %to_add) { 6; CHECK-LABEL: test_param_load: 7; CHECK: ; %bb.0: ; %main_body 8; CHECK-NEXT: s_mov_b32 m0, s0 9; CHECK-NEXT: s_mov_b32 s0, exec_lo 10; CHECK-NEXT: s_wqm_b32 exec_lo, exec_lo 11; CHECK-NEXT: lds_param_load v3, attr0.x wait_vdst:15 12; CHECK-NEXT: lds_param_load v4, attr0.y wait_vdst:15 13; CHECK-NEXT: lds_param_load v5, attr0.z wait_vdst:15 14; CHECK-NEXT: s_mov_b32 exec_lo, s0 15; CHECK-NEXT: s_waitcnt expcnt(1) 16; CHECK-NEXT: v_dual_add_f32 v0, v3, v0 :: v_dual_add_f32 v1, v4, v1 17; CHECK-NEXT: s_waitcnt expcnt(0) 18; CHECK-NEXT: v_add_f32_e32 v2, v5, v2 19; CHECK-NEXT: ; return to shader part epilog 20main_body: 21 %a = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %attr) #1 22 %b = call float @llvm.amdgcn.lds.param.load(i32 1, i32 0, i32 %attr) #1 23 %c = call float @llvm.amdgcn.lds.param.load(i32 2, i32 0, i32 %attr) #1 24 %tmp_0 = insertelement <3 x float> undef, float %a, i32 0 25 %tmp_1 = insertelement <3 x float> %tmp_0, float %b, i32 1 26 %tmp_2 = insertelement <3 x float> %tmp_1, float %c, i32 2 27 %res = fadd <3 x float> %tmp_2, %to_add 28 ret <3 x float> %res 29} 30 31; Test that s_wqm is executed before lds.direct.load. 32define amdgpu_ps <3 x float> @test_direct_load(i32 inreg %arg_0, i32 inreg %arg_1, i32 inreg %arg_2, <3 x float> %to_add) { 33; CHECK-LABEL: test_direct_load: 34; CHECK: ; %bb.0: ; %main_body 35; CHECK-NEXT: s_mov_b32 m0, s0 36; CHECK-NEXT: s_mov_b32 s0, exec_lo 37; CHECK-NEXT: s_wqm_b32 exec_lo, exec_lo 38; CHECK-NEXT: lds_direct_load v3 wait_vdst:15 39; CHECK-NEXT: s_mov_b32 m0, s1 40; CHECK-NEXT: lds_direct_load v4 wait_vdst:15 41; CHECK-NEXT: s_mov_b32 m0, s2 42; CHECK-NEXT: lds_direct_load v5 wait_vdst:15 43; CHECK-NEXT: s_mov_b32 exec_lo, s0 44; CHECK-NEXT: s_waitcnt expcnt(1) 45; CHECK-NEXT: v_dual_add_f32 v0, v3, v0 :: v_dual_add_f32 v1, v4, v1 46; CHECK-NEXT: s_waitcnt expcnt(0) 47; CHECK-NEXT: v_add_f32_e32 v2, v5, v2 48; CHECK-NEXT: ; return to shader part epilog 49main_body: 50 %a = call float @llvm.amdgcn.lds.direct.load(i32 %arg_0) #1 51 %b = call float @llvm.amdgcn.lds.direct.load(i32 %arg_1) #1 52 %c = call float @llvm.amdgcn.lds.direct.load(i32 %arg_2) #1 53 %tmp_0 = insertelement <3 x float> undef, float %a, i32 0 54 %tmp_1 = insertelement <3 x float> %tmp_0, float %b, i32 1 55 %tmp_2 = insertelement <3 x float> %tmp_1, float %c, i32 2 56 %res = fadd <3 x float> %tmp_2, %to_add 57 ret <3 x float> %res 58} 59 60attributes #1 = { nounwind readnone speculatable willreturn } 61declare float @llvm.amdgcn.lds.param.load(i32 immarg, i32 immarg, i32) #1 62declare float @llvm.amdgcn.lds.direct.load(i32) #1 63