xref: /llvm-project/llvm/test/CodeGen/AMDGPU/vopc_dpp.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
2
3define amdgpu_cs void @_amdgpu_cs_main(i32 %0) {
4; GFX11-LABEL: _amdgpu_cs_main:
5; GFX11:    v_cmp_eq_u32_e64_dpp s1, v1, v0 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
6.entry:
7  %1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 0, i32 0, i32 15, i32 15, i1 false)
8  %2 = icmp ne i32 %1, %0
9  %spec.select.3 = select i1 %2, i32 0, i32 1
10  call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %spec.select.3, ptr addrspace(8) zeroinitializer, i32 0, i32 0, i32 0)
11  ret void
12}
13
14declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg)
15declare void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32, ptr addrspace(8), i32, i32, i32 immarg)
16