xref: /llvm-project/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir (revision 042104985cc37d28db5f22f8bdf582c1108977d8)
1# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
2# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
3...
4# GCN-LABEL: name: fold_imm_non_ssa{{$}}
5# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
6# GCN: %2:vgpr_32 = V_ADD_CO_U32_e32 456, %0, implicit-def $vcc, implicit $exec
7
8name: fold_imm_non_ssa
9tracksRegLiveness: true
10registers:
11  - { id: 0, class: vgpr_32 }
12  - { id: 1, class: vgpr_32 }
13  - { id: 2, class: vgpr_32 }
14  - { id: 3, class: sreg_64 }
15body:             |
16  bb.0:
17    %0 = COPY undef %0
18    %0 = V_MOV_B32_e32 123, implicit $exec
19    %1 = V_MOV_B32_e32 456, implicit $exec
20    %2, $vcc = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
21    S_ENDPGM 0
22
23...
24# GCN-LABEL: name: fold_partially_defined_superreg{{$}}
25# GCN: %1:vgpr_32 = V_MOV_B32_e32 456, implicit $exec
26# GCN: %2:vgpr_32 = V_ADD_CO_U32_e32 123, %1, implicit-def $vcc, implicit $exec
27name: fold_partially_defined_superreg
28tracksRegLiveness: true
29registers:
30  - { id: 0, class: vgpr_32 }
31  - { id: 1, class: vgpr_32 }
32  - { id: 2, class: vgpr_32 }
33  - { id: 3, class: vreg_64 }
34body:             |
35  bb.0:
36    undef %3.sub0 = V_MOV_B32_e32 123, implicit $exec, implicit-def %3
37    %1 = V_MOV_B32_e32 456, implicit $exec
38    %2, $vcc = V_ADD_CO_U32_e64 %3.sub0, %1, 0, implicit $exec
39    S_ENDPGM 0
40
41...
42