1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O0 -mcpu=gfx1030 < %s | FileCheck %s 3 4target triple = "amdgcn-amd-amdhsa" 5 6; Unknown functions are conservatively passed all implicit parameters 7declare void @unknown_call() 8; Use the same constant as a sgpr parameter (for the kernel id) and for a vector operation 9define protected amdgpu_kernel void @kern(ptr %addr) !llvm.amdgcn.lds.kernel.id !0 { 10; CHECK-LABEL: kern: 11; CHECK: ; %bb.0: 12; CHECK-NEXT: s_mov_b32 s32, 0 13; CHECK-NEXT: s_add_u32 s12, s12, s17 14; CHECK-NEXT: s_addc_u32 s13, s13, 0 15; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12 16; CHECK-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13 17; CHECK-NEXT: s_add_u32 s0, s0, s17 18; CHECK-NEXT: s_addc_u32 s1, s1, 0 19; CHECK-NEXT: ; implicit-def: $vgpr40 : SGPR spill to VGPR lane 20; CHECK-NEXT: v_writelane_b32 v40, s16, 0 21; CHECK-NEXT: s_mov_b32 s13, s15 22; CHECK-NEXT: s_mov_b32 s12, s14 23; CHECK-NEXT: v_readlane_b32 s14, v40, 0 24; CHECK-NEXT: s_mov_b64 s[16:17], s[8:9] 25; CHECK-NEXT: s_load_dwordx2 s[8:9], s[16:17], 0x0 26; CHECK-NEXT: v_mov_b32_e32 v5, 42 27; CHECK-NEXT: s_waitcnt lgkmcnt(0) 28; CHECK-NEXT: v_mov_b32_e32 v3, s8 29; CHECK-NEXT: v_mov_b32_e32 v4, s9 30; CHECK-NEXT: flat_store_dword v[3:4], v5 31; CHECK-NEXT: s_mov_b64 s[18:19], 8 32; CHECK-NEXT: s_mov_b32 s8, s16 33; CHECK-NEXT: s_mov_b32 s9, s17 34; CHECK-NEXT: s_mov_b32 s16, s18 35; CHECK-NEXT: s_mov_b32 s15, s19 36; CHECK-NEXT: s_add_u32 s8, s8, s16 37; CHECK-NEXT: s_addc_u32 s15, s9, s15 38; CHECK-NEXT: ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9 39; CHECK-NEXT: s_mov_b32 s9, s15 40; CHECK-NEXT: s_getpc_b64 s[16:17] 41; CHECK-NEXT: s_add_u32 s16, s16, unknown_call@gotpcrel32@lo+4 42; CHECK-NEXT: s_addc_u32 s17, s17, unknown_call@gotpcrel32@hi+12 43; CHECK-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 44; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3] 45; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1] 46; CHECK-NEXT: s_mov_b32 s15, 20 47; CHECK-NEXT: v_lshlrev_b32_e64 v2, s15, v2 48; CHECK-NEXT: s_mov_b32 s15, 10 49; CHECK-NEXT: v_lshlrev_b32_e64 v1, s15, v1 50; CHECK-NEXT: v_or3_b32 v31, v0, v1, v2 51; CHECK-NEXT: s_mov_b32 s15, 42 52; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21] 53; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23] 54; CHECK-NEXT: s_waitcnt lgkmcnt(0) 55; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] 56; CHECK-NEXT: s_endpgm 57 store i32 42, ptr %addr 58 call fastcc void @unknown_call() 59 ret void 60} 61 62!llvm.module.flags = !{!1} 63!0 = !{i32 42} 64!1 = !{i32 1, !"amdhsa_code_object_version", i32 500} 65