1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 3; GCN-LABEL: {{^}}load_idx_idy: 4; GCN-NOT: global_load 5; GCN: s_load_dword [[ID_XY:s[0-9]+]], s[4:5], 0x4 6; GCN-NOT: global_load 7; GCN: s_lshr_b32 [[ID_Y:s[0-9]+]], [[ID_XY]], 16 8; GCN: s_add_i32 [[ID_SUM:s[0-9]+]], [[ID_Y]], [[ID_XY]] 9; GCN: s_and_b32 s{{[0-9]+}}, [[ID_SUM]], 0xffff 10define protected amdgpu_kernel void @load_idx_idy(ptr addrspace(1) %out) { 11entry: 12 %disp = tail call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 13 %gep_x = getelementptr i8, ptr addrspace(4) %disp, i64 4 14 %id_x = load i16, ptr addrspace(4) %gep_x, align 4, !invariant.load !0 ; load workgroup size x 15 %gep_y = getelementptr i8, ptr addrspace(4) %disp, i64 6 16 %id_y = load i16, ptr addrspace(4) %gep_y, align 2, !invariant.load !0 ; load workgroup size y 17 %add = add nuw nsw i16 %id_y, %id_x 18 %conv = zext i16 %add to i32 19 store i32 %conv, ptr addrspace(1) %out, align 4 20 ret void 21} 22 23; A little more complicated case where more sub-dword loads could be coalesced 24; if they are not widening earlier. 25; GCN-LABEL: {{^}}load_4i16: 26; GCN: s_load_dwordx2 s[[[D0:[0-9]+]]:[[D1:[0-9]+]]], s[4:5], 0x4 27; GCN-NOT: s_load_dword {{s[0-9]+}}, s[4:5], 0x4 28; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D0]], 16 29; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D1]], 16 30; GCN: s_endpgm 31define protected amdgpu_kernel void @load_4i16(ptr addrspace(1) %out) { 32entry: 33 %disp = tail call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 34 %gep_x = getelementptr i8, ptr addrspace(4) %disp, i64 4 35 %id_x = load i16, ptr addrspace(4) %gep_x, align 4, !invariant.load !0 ; load workgroup size x 36 %gep_y = getelementptr i8, ptr addrspace(4) %disp, i64 6 37 %id_y = load i16, ptr addrspace(4) %gep_y, align 2, !invariant.load !0 ; load workgroup size y 38 %gep_z = getelementptr i8, ptr addrspace(4) %disp, i64 8 39 %id_z = load i16, ptr addrspace(4) %gep_z, align 4, !invariant.load !0 ; load workgroup size x 40 %gep_w = getelementptr i8, ptr addrspace(4) %disp, i64 10 41 %id_w = load i16, ptr addrspace(4) %gep_w, align 2, !invariant.load !0 ; load workgroup size y 42 %add = add nuw nsw i16 %id_y, %id_x 43 %add2 = add nuw nsw i16 %id_z, %id_w 44 %add3 = add nuw nsw i16 %add, %add2 45 %conv = zext i16 %add3 to i32 46 store i32 %conv, ptr addrspace(1) %out, align 4 47 ret void 48} 49 50declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 51 52!0 = !{!0} 53