1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize64 --global-isel=0 -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK %s 3 4define amdgpu_kernel void @icmp_test() { 5; CHECK-LABEL: icmp_test: 6; CHECK: ; %bb.0: ; %entry 7; CHECK-NEXT: v_cmp_eq_u16_e64 s[0:1], 0, 0 8; CHECK-NEXT: v_mov_b32_e32 v1, 0 9; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) 10; CHECK-NEXT: s_cmp_eq_u64 s[0:1], 0 11; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 12; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] 13; CHECK-NEXT: ds_store_b32 v1, v0 14; CHECK-NEXT: s_endpgm 15entry: 16 %icmp.intr = tail call i64 @llvm.amdgcn.icmp.i64.i16(i16 0, i16 0, i32 32) 17 %cmp0 = icmp eq i64 %icmp.intr, 0 18 %zext0 = zext i1 %cmp0 to i32 19 store i32 %zext0, ptr addrspace(3) null, align 2147483648 20 ret void 21} 22 23define amdgpu_kernel void @fcmp_test(half %x, half %y) { 24; CHECK-LABEL: fcmp_test: 25; CHECK: ; %bb.0: ; %entry 26; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x0 27; CHECK-NEXT: v_mov_b32_e32 v1, 0 28; CHECK-NEXT: s_waitcnt lgkmcnt(0) 29; CHECK-NEXT: s_lshr_b32 s1, s0, 16 30; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) 31; CHECK-NEXT: v_cmp_le_f16_e64 s[0:1], s0, s1 32; CHECK-NEXT: s_cmp_eq_u64 s[0:1], 0 33; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 34; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) 35; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] 36; CHECK-NEXT: ds_store_b32 v1, v0 37; CHECK-NEXT: s_endpgm 38entry: 39 %fcmp.intr = tail call i64 @llvm.amdgcn.fcmp.i64.f16(half %x, half %y, i32 5) 40 %cmp0 = icmp eq i64 %fcmp.intr, 0 41 %zext0 = zext i1 %cmp0 to i32 42 store i32 %zext0, ptr addrspace(3) null, align 2147483648 43 ret void 44} 45 46define amdgpu_kernel void @ballot_test(half %x, half %y) { 47; CHECK-LABEL: ballot_test: 48; CHECK: ; %bb.0: 49; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x0 50; CHECK-NEXT: v_mov_b32_e32 v2, 0 51; CHECK-NEXT: s_waitcnt lgkmcnt(0) 52; CHECK-NEXT: s_lshr_b32 s1, s0, 16 53; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) 54; CHECK-NEXT: v_cmp_eq_f16_e64 s[0:1], s0, s1 55; CHECK-NEXT: v_mov_b32_e32 v0, s0 56; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) 57; CHECK-NEXT: v_mov_b32_e32 v1, s1 58; CHECK-NEXT: ds_store_b64 v2, v[0:1] 59; CHECK-NEXT: s_endpgm 60 %cmp = fcmp oeq half %x, %y 61 %ballot = tail call i64 @llvm.amdgcn.ballot.i64(i1 %cmp) 62 store i64 %ballot, ptr addrspace(3) null, align 2147483648 63 ret void 64} 65 66declare i64 @llvm.amdgcn.icmp.i64.i16(i16, i16, i32 immarg) #0 67 68declare i64 @llvm.amdgcn.fcmp.i64.f16(half, half, i32 immarg) #0 69 70declare i64 @llvm.amdgcn.ballot.i64(i1) #0 71 72attributes #0 = { convergent nounwind readnone willreturn } 73