1; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck %s 2; RUN: llc -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s 4 5; On gfx6 and gfx7, this test shows a bug in SelectionDAG where scalarizing the 6; extension of a vector of f16 generates an illegal node that errors later. 7 8; CHECK-LABEL: {{^}}main: 9; CHECK: v_cvt_f32_f16 10 11define amdgpu_gs void @main(i32 inreg %arg) local_unnamed_addr #0 { 12.entry: 13 %tmp = load volatile float, ptr addrspace(1) undef 14 %tmp1 = bitcast float %tmp to i32 15 %im0.i = lshr i32 %tmp1, 16 16 %tmp2 = insertelement <2 x i32> undef, i32 %im0.i, i32 1 17 %tmp3 = trunc <2 x i32> %tmp2 to <2 x i16> 18 %tmp4 = bitcast <2 x i16> %tmp3 to <2 x half> 19 %tmp5 = fpext <2 x half> %tmp4 to <2 x float> 20 %bc = bitcast <2 x float> %tmp5 to <2 x i32> 21 %tmp6 = extractelement <2 x i32> %bc, i32 1 22 store volatile i32 %tmp6, ptr addrspace(1) undef 23 ret void 24} 25 26attributes #0 = { nounwind } 27