1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -stop-after=amdgpu-isel < %s | FileCheck %s 3 4@external_constant1 = external addrspace(4) constant float, align 4 5@external_constant2 = external addrspace(1) constant float, align 4 6@const.ptr = external addrspace(4) constant ptr, align 4 7 8define void @test() { 9 ; CHECK-LABEL: name: test 10 ; CHECK: bb.0.entry: 11 ; CHECK-NEXT: successors: %bb.1(0x30000000), %bb.3(0x50000000) 12 ; CHECK-NEXT: {{ $}} 13 ; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant1, target-flags(amdgpu-gotprel32-hi) @external_constant1, implicit-def dead $scc 14 ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4) 15 ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed [[S_LOAD_DWORDX2_IMM]], 0, 0 :: (dereferenceable invariant load (s32) from @external_constant1, addrspace 4) 16 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 17 ; CHECK-NEXT: nofpexcept S_CMP_LG_F32 killed [[S_LOAD_DWORD_IMM]], killed [[S_MOV_B32_]], implicit-def $scc, implicit $mode 18 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit $scc 19 ; CHECK-NEXT: S_BRANCH %bb.1 20 ; CHECK-NEXT: {{ $}} 21 ; CHECK-NEXT: bb.1.bb1: 22 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) 23 ; CHECK-NEXT: {{ $}} 24 ; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET1:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @const.ptr, target-flags(amdgpu-gotprel32-hi) @const.ptr, implicit-def dead $scc 25 ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET1]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4) 26 ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM2:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM killed [[S_LOAD_DWORDX2_IMM1]], 0, 0 :: (invariant load (s64) from @const.ptr, addrspace 4) 27 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 28 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed [[S_LOAD_DWORDX2_IMM2]], killed [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load (s32) from %ir.0, addrspace 1) 29 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 1092616192 30 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 1065353216 31 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[GLOBAL_LOAD_DWORD_SADDR]] 32 ; CHECK-NEXT: nofpexcept S_CMP_LT_F32 killed [[COPY]], killed [[S_MOV_B32_2]], implicit-def $scc, implicit $mode 33 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.4, implicit $scc 34 ; CHECK-NEXT: S_BRANCH %bb.2 35 ; CHECK-NEXT: {{ $}} 36 ; CHECK-NEXT: bb.2.bb2: 37 ; CHECK-NEXT: successors: %bb.4(0x80000000) 38 ; CHECK-NEXT: {{ $}} 39 ; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 40 ; CHECK-NEXT: S_BRANCH %bb.4 41 ; CHECK-NEXT: {{ $}} 42 ; CHECK-NEXT: bb.3.Flow1: 43 ; CHECK-NEXT: successors: %bb.7(0x80000000) 44 ; CHECK-NEXT: {{ $}} 45 ; CHECK-NEXT: S_BRANCH %bb.7 46 ; CHECK-NEXT: {{ $}} 47 ; CHECK-NEXT: bb.4.bb3: 48 ; CHECK-NEXT: successors: %bb.5(0x50000000), %bb.6(0x30000000) 49 ; CHECK-NEXT: {{ $}} 50 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sgpr_32 = PHI [[S_MOV_B32_1]], %bb.1, [[S_MOV_B32_3]], %bb.2 51 ; CHECK-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 52 ; CHECK-NEXT: nofpexcept S_CMP_NEQ_F32 [[PHI]], killed [[S_MOV_B32_4]], implicit-def $scc, implicit $mode 53 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.6, implicit $scc 54 ; CHECK-NEXT: S_BRANCH %bb.5 55 ; CHECK-NEXT: {{ $}} 56 ; CHECK-NEXT: bb.5.bb4: 57 ; CHECK-NEXT: successors: %bb.6(0x80000000) 58 ; CHECK-NEXT: {{ $}} 59 ; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET2:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant2, target-flags(amdgpu-gotprel32-hi) @external_constant2, implicit-def dead $scc 60 ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM3:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET2]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4) 61 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 62 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1082130432, implicit $exec 63 ; CHECK-NEXT: GLOBAL_STORE_DWORD_SADDR killed [[V_MOV_B32_e32_1]], killed [[V_MOV_B32_e32_2]], killed [[S_LOAD_DWORDX2_IMM3]], 0, 0, implicit $exec :: (store (s32) into @external_constant2, addrspace 1) 64 ; CHECK-NEXT: {{ $}} 65 ; CHECK-NEXT: bb.6.Flow: 66 ; CHECK-NEXT: successors: %bb.3(0x80000000) 67 ; CHECK-NEXT: {{ $}} 68 ; CHECK-NEXT: S_BRANCH %bb.3 69 ; CHECK-NEXT: {{ $}} 70 ; CHECK-NEXT: bb.7.bb5: 71 ; CHECK-NEXT: SI_RETURN 72entry: 73 %ld1 = load float, ptr addrspace(4) @external_constant1 74 %cmp1 = fcmp one float %ld1, 0.0 75 br i1 %cmp1, label %bb5, label %bb1, !amdgpu.uniform !0 76 77bb1: 78 %ptr = load ptr, ptr addrspace(4) @const.ptr 79 %ld2 = load float, ptr %ptr, align 4 80 %cmp2 = fcmp olt float %ld2, 1.0 81 %or = or i1 %cmp2, false 82 br i1 %or, label %bb3, label %bb2, !amdgpu.uniform !0 83 84bb2: 85 br label %bb3 86 87bb3: 88 %phi = phi float [ 10.0, %bb1 ], [ 0.0, %bb2 ] 89 %cmp3 = fcmp oeq float %phi, 0.0 90 br i1 %cmp3, label %bb4, label %bb5, !amdgpu.uniform !0 91 92bb4: 93 store float 4.0, ptr addrspace(1) @external_constant2 94 br label %bb5 95 96bb5: 97 ret void 98} 99 100!0 = !{} 101