1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -verify-coalescing -run-pass=register-coalescer -o - %s | FileCheck %s 3 4# The copy from %0 to %1 introduces liveness for %3.sub2. After 5# coalescing, the use of %1.sub2 needs to be marked undef. The 6# subregless copy previously did not consider the existing subregister 7# on the use operand. 8 9--- 10name: undef_subreg_use_after_full_copy_coalesce_0 11tracksRegLiveness: true 12body: | 13 bb.0: 14 ; CHECK-LABEL: name: undef_subreg_use_after_full_copy_coalesce_0 15 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec 16 ; CHECK-NEXT: dead [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec 17 ; CHECK-NEXT: S_ENDPGM 0, implicit undef [[V_MOV_B32_e32_]].sub2 18 undef %0.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec 19 %0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec 20 %1:vreg_96 = COPY killed %0 21 S_ENDPGM 0, implicit %1.sub2 22 23... 24 25# Same, except coalesced copy has a subregister index that needs to be 26# composed with the use index. 27--- 28name: undef_subreg_use_after_full_copy_coalesce_composed 29tracksRegLiveness: true 30body: | 31 bb.0: 32 ; CHECK-LABEL: name: undef_subreg_use_after_full_copy_coalesce_composed 33 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec 34 ; CHECK-NEXT: dead [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec 35 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF 36 ; CHECK-NEXT: S_ENDPGM 0, implicit [[DEF]].sub1 37 undef %0.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec 38 %0.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec 39 %1:vreg_128 = COPY killed %0 40 %2:vreg_64 = COPY killed %1.sub2_sub3 41 S_ENDPGM 0, implicit %2.sub1 42 43... 44 45# FIXME: Initial computed range is wrong for %0.sub2_sub3 and fails 46# verifier. 47# --- 48# name: undef_subreg_use_after_full_copy_coalesce_composed2 49# tracksRegLiveness: true 50# body: | 51# bb.0: 52# undef %0.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec 53# %0.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec 54# %1:vreg_128 = COPY killed %0.sub2_sub3 55# S_ENDPGM 0, implicit %1.sub1 56 57# ... 58 59--- 60name: undef_subreg_use_after_full_copy_coalesce_1 61tracksRegLiveness: true 62body: | 63 bb.0: 64 liveins: $vgpr0, $vgpr1, $vgpr2 65 66 ; CHECK-LABEL: name: undef_subreg_use_after_full_copy_coalesce_1 67 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 68 ; CHECK-NEXT: {{ $}} 69 ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_96 = COPY $vgpr0 70 ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_96 = COPY $vgpr1 71 ; CHECK-NEXT: S_NOP 0, implicit undef [[COPY]].sub2 72 ; CHECK-NEXT: S_NOP 0, implicit [[COPY]].sub1 73 ; CHECK-NEXT: S_ENDPGM 0 74 %0:vgpr_32 = COPY killed $vgpr0 75 %1:vgpr_32 = COPY killed $vgpr1 76 undef %2.sub0:vreg_96 = COPY killed %0 77 %2.sub1:vreg_96 = COPY killed %1 78 %3:vreg_96 = COPY killed %2 79 S_NOP 0, implicit %3.sub2 80 S_NOP 0, implicit %3.sub1 81 S_ENDPGM 0 82 83... 84