xref: /llvm-project/llvm/test/CodeGen/AMDGPU/swdev282079.mir (revision 8871c3c562690347d75190be758312d1f92a7db4)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -o - %s | FileCheck %s
3
4# This was attempting to look back through the REG_SEQUENCE source
5# operands and trying to look for physreg defs.
6
7---
8name: fold_reg_sequence_of_copy_from_physreg_0
9tracksRegLiveness: true
10machineFunctionInfo:
11  isEntryFunction: true
12  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
13  stackPtrOffsetReg: '$sgpr32'
14  occupancy:       8
15body:             |
16  bb.0:
17    ; CHECK-LABEL: name: fold_reg_sequence_of_copy_from_physreg_0
18    ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
19    ; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
20    ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
21    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
22    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
23    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
24    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
25    ; CHECK-NEXT: FLAT_STORE_DWORDX2 killed [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
26    ; CHECK-NEXT: S_ENDPGM 0
27    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
28    $vgpr1 = V_MOV_B32_e32 1, implicit $exec
29    S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
30    %0:vgpr_32 = COPY $vgpr0
31    %1:vgpr_32 = COPY $vgpr1
32    %2:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
33    %3:vreg_64_align2 = IMPLICIT_DEF
34    FLAT_STORE_DWORDX2 killed %3, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
35    S_ENDPGM 0
36
37...
38
39---
40name: fold_reg_sequence_of_copy_from_physreg_1
41tracksRegLiveness: true
42machineFunctionInfo:
43  isEntryFunction: true
44  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
45  stackPtrOffsetReg: '$sgpr32'
46  occupancy:       8
47body:             |
48  bb.0:
49    ; CHECK-LABEL: name: fold_reg_sequence_of_copy_from_physreg_1
50    ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
51    ; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
52    ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
53    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
54    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
55    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
56    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
57    ; CHECK-NEXT: FLAT_STORE_DWORDX2 killed [[REG_SEQUENCE]], killed [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
58    ; CHECK-NEXT: S_ENDPGM 0
59    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
60    $vgpr1 = V_MOV_B32_e32 1, implicit $exec
61    S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
62    %0:vgpr_32 = COPY $vgpr0
63    %1:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
64    %2:vgpr_32 = COPY %0
65    %3:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %2, %subreg.sub1
66    %4:vreg_64_align2 = IMPLICIT_DEF
67    FLAT_STORE_DWORDX2 killed %3, killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
68    S_ENDPGM 0
69
70...
71
72---
73name: fold_reg_sequence_of_copy_from_physreg_2
74tracksRegLiveness: true
75machineFunctionInfo:
76  isEntryFunction: true
77  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
78  stackPtrOffsetReg: '$sgpr32'
79  occupancy:       8
80body:             |
81  bb.0:
82    ; CHECK-LABEL: name: fold_reg_sequence_of_copy_from_physreg_2
83    ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
84    ; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
85    ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
86    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
87    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
88    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[COPY]], %subreg.sub1
89    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
90    ; CHECK-NEXT: FLAT_STORE_DWORDX2 killed [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
91    ; CHECK-NEXT: S_ENDPGM 0
92    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
93    $vgpr1 = V_MOV_B32_e32 1, implicit $exec
94    S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
95    %0:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
96    %1:vgpr_32 = COPY $vgpr0
97    %2:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
98    %3:vreg_64_align2 = IMPLICIT_DEF
99    FLAT_STORE_DWORDX2 killed %3, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
100    S_ENDPGM 0
101
102...
103
104# This would crash looking for a def in any mayLoad instruction
105---
106name: fold_inlineasm_def
107tracksRegLiveness: true
108body:             |
109  bb.0:
110
111    ; CHECK-LABEL: name: fold_inlineasm_def
112    ; CHECK: INLINEASM &"s_waitcnt vmcnt($0)", 41 /* sideeffect mayload isconvergent attdialect */, 13 /* imm */, 0
113    ; CHECK-NEXT: S_ENDPGM 0
114    INLINEASM &"s_waitcnt vmcnt($0)", 41 /* sideeffect mayload isconvergent attdialect */, 13 /* imm */, 0
115    S_ENDPGM 0
116
117...
118