xref: /llvm-project/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir (revision abde52aa667118d18e9551ab87a15b95c267b3b6)
1# RUN: llc -mtriple=amdgcn -run-pass liveintervals -debug-only=regalloc -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
2# RUN: llc -mtriple=amdgcn --passes='print<live-intervals>' -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
3# REQUIRES: asserts
4
5# CHECK: INTERVALS
6# CHECK: %0
7# CHECK-LABEL: Machine code for function test1:
8
9--- |
10  define amdgpu_kernel void @test1() { ret void }
11...
12---
13name: test1
14registers:
15  - { id: 0, class: sreg_64 }
16body: |
17  bb.0:
18    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
19    S_BRANCH %bb.2
20
21  bb.1:
22    S_NOP 0, implicit-def undef %0.sub0
23    S_BRANCH %bb.3
24
25  bb.2:
26    S_NOP 0, implicit-def %0
27    S_BRANCH %bb.3
28
29  bb.3:
30    S_NOP 0
31    S_NOP 0, implicit %0
32...
33