1; RUN: opt -S --amdgpu-annotate-uniform < %s | FileCheck -check-prefix=OPT %s 2target datalayout = "A5" 3 4; "load vaddr" depends on the store, so we should not mark vaddr as amdgpu.noclobber. 5 6; OPT-LABEL: @store_clobbers_load( 7; OPT: %zero = load <4 x i32>, ptr addrspace(1) %input, align 16{{$}} 8define amdgpu_kernel void @store_clobbers_load(ptr addrspace(1) %input, ptr addrspace(1) %out, i32 %index) { 9entry: 10 store i32 0, ptr addrspace(1) %input 11 %zero = load <4 x i32>, ptr addrspace(1) %input, align 16 12 %one = insertelement <4 x i32> %zero, i32 1, i32 1 13 %two = insertelement <4 x i32> %one, i32 2, i32 2 14 %three = insertelement <4 x i32> %two, i32 3, i32 3 15 store <4 x i32> %three, ptr addrspace(1) %input, align 16 16 %rslt = extractelement <4 x i32> %three, i32 %index 17 store i32 %rslt, ptr addrspace(1) %out, align 4 18 ret void 19} 20 21 22declare i32 @llvm.amdgcn.workitem.id.x() 23@lds0 = addrspace(3) global [512 x i32] undef, align 4 24 25; To check that %arrayidx0 is not marked as amdgpu.noclobber. 26 27; OPT-LABEL: @atomicrmw_clobbers_load( 28; OPT: %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.0, !amdgpu.uniform !0 29; OPT-NEXT: %val = atomicrmw xchg ptr addrspace(3) %arrayidx0, i32 3 seq_cst 30 31define amdgpu_kernel void @atomicrmw_clobbers_load(ptr addrspace(1) %out0, ptr addrspace(1) %out1) { 32 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 33 %idx.0 = add nsw i32 %tid.x, 2 34 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.0 35 %val = atomicrmw xchg ptr addrspace(3) %arrayidx0, i32 3 seq_cst 36 %load = load i32, ptr addrspace(3) %arrayidx0, align 4 37 store i32 %val, ptr addrspace(1) %out0, align 4 38 store i32 %load, ptr addrspace(1) %out1, align 4 39 ret void 40} 41