1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 2# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass liveintervals,phi-node-elimination -o - %s | FileCheck -check-prefixes=GCN %s 3# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 --passes='require<live-intervals>,phi-node-elimination' -verify-each -o - %s | FileCheck -check-prefixes=GCN %s 4 5# This checks liveintervals pass verification and phi-node-elimination correctly preserves them. 6 7--- 8name: split_critical_edge_subranges 9tracksRegLiveness: true 10body: | 11 ; GCN-LABEL: name: split_critical_edge_subranges 12 ; GCN: bb.0: 13 ; GCN-NEXT: successors: %bb.5(0x40000000), %bb.1(0x40000000) 14 ; GCN-NEXT: {{ $}} 15 ; GCN-NEXT: %coord:vreg_64 = IMPLICIT_DEF 16 ; GCN-NEXT: %desc:sgpr_256 = IMPLICIT_DEF 17 ; GCN-NEXT: %c0:sreg_32 = IMPLICIT_DEF 18 ; GCN-NEXT: %c1:sreg_32 = IMPLICIT_DEF 19 ; GCN-NEXT: %const:vgpr_32 = IMPLICIT_DEF 20 ; GCN-NEXT: %load:vreg_64 = IMAGE_LOAD_V2_V2_gfx11 %coord, %desc, 3, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s64), align 16, addrspace 4) 21 ; GCN-NEXT: %s0a:vgpr_32 = COPY %load.sub0 22 ; GCN-NEXT: %s0b:vgpr_32 = COPY %load.sub1 23 ; GCN-NEXT: S_CMP_EQ_U32 %c0, %c1, implicit-def $scc 24 ; GCN-NEXT: S_CBRANCH_SCC0 %bb.1, implicit $scc 25 ; GCN-NEXT: {{ $}} 26 ; GCN-NEXT: bb.5: 27 ; GCN-NEXT: successors: %bb.3(0x80000000) 28 ; GCN-NEXT: {{ $}} 29 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY %s0a 30 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY %s0b 31 ; GCN-NEXT: S_BRANCH %bb.3 32 ; GCN-NEXT: {{ $}} 33 ; GCN-NEXT: bb.1: 34 ; GCN-NEXT: successors: %bb.3(0x80000000) 35 ; GCN-NEXT: {{ $}} 36 ; GCN-NEXT: %s0c:vgpr_32 = V_ADD_F32_e64 0, %s0a, 0, %const, 0, 0, implicit $mode, implicit $exec 37 ; GCN-NEXT: %s0d:vgpr_32 = V_ADD_F32_e64 0, %s0b, 0, %const, 0, 0, implicit $mode, implicit $exec 38 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY %s0c 39 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY %s0d 40 ; GCN-NEXT: S_BRANCH %bb.3 41 ; GCN-NEXT: {{ $}} 42 ; GCN-NEXT: bb.2: 43 ; GCN-NEXT: S_NOP 0 44 ; GCN-NEXT: S_ENDPGM 0 45 ; GCN-NEXT: {{ $}} 46 ; GCN-NEXT: bb.3: 47 ; GCN-NEXT: successors: %bb.4(0x80000000) 48 ; GCN-NEXT: {{ $}} 49 ; GCN-NEXT: %phi1:vgpr_32 = COPY [[COPY1]] 50 ; GCN-NEXT: %phi0:vgpr_32 = COPY [[COPY]] 51 ; GCN-NEXT: S_BRANCH %bb.4 52 ; GCN-NEXT: {{ $}} 53 ; GCN-NEXT: bb.4: 54 ; GCN-NEXT: S_ENDPGM 0, implicit %phi0, implicit %phi1 55 bb.0: 56 %coord:vreg_64 = IMPLICIT_DEF 57 %desc:sgpr_256 = IMPLICIT_DEF 58 %c0:sreg_32 = IMPLICIT_DEF 59 %c1:sreg_32 = IMPLICIT_DEF 60 %const:vgpr_32 = IMPLICIT_DEF 61 %load:vreg_64 = IMAGE_LOAD_V2_V2_gfx11 %coord:vreg_64, killed %desc:sgpr_256, 3, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s64), align 16, addrspace 4) 62 %s0a:vgpr_32 = COPY %load.sub0:vreg_64 63 %s0b:vgpr_32 = COPY %load.sub1:vreg_64 64 S_CMP_EQ_U32 killed %c0:sreg_32, killed %c1:sreg_32, implicit-def $scc 65 S_CBRANCH_SCC1 %bb.3, implicit $scc 66 S_BRANCH %bb.1 67 68 bb.1: 69 %s0c:vgpr_32 = V_ADD_F32_e64 0, %s0a:vgpr_32, 0, %const:vgpr_32, 0, 0, implicit $mode, implicit $exec 70 %s0d:vgpr_32 = V_ADD_F32_e64 0, %s0b:vgpr_32, 0, %const:vgpr_32, 0, 0, implicit $mode, implicit $exec 71 S_BRANCH %bb.3 72 73 bb.2: 74 S_NOP 0 75 S_ENDPGM 0 76 77 bb.3: 78 %phi0:vgpr_32 = PHI %s0a:vgpr_32, %bb.0, %s0c:vgpr_32, %bb.1 79 %phi1:vgpr_32 = PHI %s0b:vgpr_32, %bb.0, %s0d:vgpr_32, %bb.1 80 S_BRANCH %bb.4 81 82 bb.4: 83 S_ENDPGM 0, implicit %phi0:vgpr_32, implicit %phi1:vgpr_32 84... 85