xref: /llvm-project/llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll (revision d85e849ff4d5e03ed83ee10e56074f238ba444d3)
1; RUN: llc  -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
2
3; GCN-LABEL: ; %bb.0:
4; GCN: s_load_dword s{{[0-9]+}}, s[[[ADDR_LO:[0-9]+]]{{\:}}[[ADDR_HI:[0-9]+]]], 0x0
5; GCN: s_waitcnt lgkmcnt(0)
6; GCN: global_store_dword v
7
8define amdgpu_kernel void @zot(ptr addrspace(1) nocapture %arg, ptr addrspace(1) nocapture %arg1) {
9bb:
10  %tmp = call i32 @llvm.amdgcn.workitem.id.x()
11  %tmp2 = icmp eq i32 %tmp, 0
12  br i1 %tmp2, label %bb3, label %bb8
13
14bb3:                                              ; preds = %bb
15  %tmp4 = load i32, ptr addrspace(1) %arg, align 4
16  store i32 0, ptr addrspace(1) %arg, align 4
17  %tmp5 = zext i32 %tmp4 to i64
18  %tmp6 = load i64, ptr addrspace(1) %arg1, align 8
19  %tmp7 = add i64 %tmp6, %tmp5
20  store i64 %tmp7, ptr addrspace(1) %arg1, align 8
21  br label %bb8
22
23bb8:                                              ; preds = %bb3, %bb
24  ret void
25}
26; Function Attrs: nounwind readnone speculatable
27declare i32 @llvm.amdgcn.workitem.id.x() #0
28
29attributes #0 = { nounwind readnone speculatable }
30