xref: /llvm-project/llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
2
3# GCN-LABEL: name: smrd_vgpr_offset_imm
4# GCN: V_READFIRSTLANE_B32
5# GCN: S_BUFFER_LOAD_DWORD_SGPR
6---
7name:            smrd_vgpr_offset_imm
8body:             |
9  bb.0:
10    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
11
12    %4:vgpr_32 = COPY $vgpr0
13    %3:sgpr_32 = COPY $sgpr3
14    %2:sgpr_32 = COPY $sgpr2
15    %1:sgpr_32 = COPY $sgpr1
16    %0:sgpr_32 = COPY $sgpr0
17    %5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
18    %6:sreg_32_xm0 = S_MOV_B32 4095
19    %8:vgpr_32 = COPY %6
20    %7:vgpr_32 = V_ADD_CO_U32_e32 %4, killed %8, implicit-def dead $vcc, implicit $exec
21    %10:sreg_32 = COPY %7
22    %9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0
23    $vgpr0 = COPY %9
24    SI_RETURN_TO_EPILOG $vgpr0
25...
26
27# GCN-LABEL: name: smrd_vgpr_offset_imm_add_u32
28# GCN: V_READFIRSTLANE_B32
29# GCN: S_BUFFER_LOAD_DWORD_SGPR
30---
31name:            smrd_vgpr_offset_imm_add_u32
32body:             |
33  bb.0:
34    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
35
36    %4:vgpr_32 = COPY $vgpr0
37    %3:sgpr_32 = COPY $sgpr3
38    %2:sgpr_32 = COPY $sgpr2
39    %1:sgpr_32 = COPY $sgpr1
40    %0:sgpr_32 = COPY $sgpr0
41    %5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
42    %6:sreg_32_xm0 = S_MOV_B32 4095
43    %8:vgpr_32 = COPY %6
44    %7:vgpr_32 = V_ADD_U32_e32 %4, killed %8, implicit $exec
45    %10:sreg_32 = COPY %7
46    %9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0 :: (dereferenceable invariant load (s32))
47    $vgpr0 = COPY %9
48    SI_RETURN_TO_EPILOG $vgpr0
49
50...
51