1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s 3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -passes si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s 4 5# Skip folding a REG_SEQUENCE to its user when the regclasses for the user operands can't be 6# fully determined from the instruction description. 7--- 8name: regsequence_with_regsequence_use_op 9tracksRegLiveness: true 10body: | 11 bb.0: 12 liveins: $agpr0, $agpr1 13 14 ; GCN-LABEL: name: regsequence_with_regsequence_use_op 15 ; GCN: liveins: $agpr0, $agpr1 16 ; GCN-NEXT: {{ $}} 17 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0 18 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1 19 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 20 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF 21 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF]], %subreg.sub2 22 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]] 23 %0:vgpr_32 = COPY $agpr0 24 %1:vgpr_32 = COPY $agpr1 25 %2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1 26 %3:vgpr_32 = IMPLICIT_DEF 27 %4:vreg_96_align2 = REG_SEQUENCE killed %2:vreg_64_align2, %subreg.sub0_sub1, killed %3:vgpr_32, %subreg.sub2 28 S_ENDPGM 0, implicit %4 29... 30--- 31name: insert_subreg_with_regsequence_use_op 32tracksRegLiveness: true 33body: | 34 bb.0: 35 liveins: $agpr0, $agpr1 36 37 ; GCN-LABEL: name: insert_subreg_with_regsequence_use_op 38 ; GCN: liveins: $agpr0, $agpr1 39 ; GCN-NEXT: {{ $}} 40 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0 41 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1 42 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 43 ; GCN-NEXT: S_NOP 0, implicit-def %3 44 ; GCN-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64_align2 = INSERT_SUBREG %3, [[REG_SEQUENCE]], %subreg.sub0_sub1 45 ; GCN-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 46 %0:vgpr_32 = COPY $agpr0 47 %1:vgpr_32 = COPY $agpr1 48 %2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1 49 S_NOP 0, implicit-def %3:vreg_64_align2 50 %4:vreg_64_align2 = INSERT_SUBREG %3, %2, %subreg.sub0_sub1 51 S_ENDPGM 0, implicit %4 52... 53