1; FIXME: The si scheduler crashes if when lane mask tracking is enabled, so 2; we need to disable this when the si scheduler is being used. 3; The only way the subtarget knows that the si machine scheduler is being used 4; is to specify -mattr=si-scheduler. If we just pass --misched=si, the backend 5; won't know what scheduler we are using. 6; RUN: llc -mtriple=amdgcn -mcpu=tahiti --misched=si -mattr=si-scheduler < %s | FileCheck %s 7; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 --misched=si -mattr=si-scheduler < %s | FileCheck %s 8 9; The test checks the "si" machine scheduler pass works correctly. 10 11; CHECK-LABEL: {{^}}main: 12; CHECK: s_wqm 13; CHECK: s_load_dwordx8 14; CHECK: s_load_dwordx4 15; CHECK: s_waitcnt lgkmcnt(0) 16; CHECK: image_sample 17; CHECK: s_waitcnt vmcnt(0) 18; CHECK: exp 19; CHECK: s_endpgm 20define amdgpu_ps void @main(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { 21main_body: 22 %tmp22 = load <32 x i8>, ptr addrspace(4) %arg3, align 32, !tbaa !0 23 %tmp24 = load <16 x i8>, ptr addrspace(4) %arg2, align 16, !tbaa !0 24 %i.i = extractelement <2 x i32> %arg11, i32 0 25 %j.i = extractelement <2 x i32> %arg11, i32 1 26 %i.f.i = bitcast i32 %i.i to float 27 %j.f.i = bitcast i32 %j.i to float 28 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #1 29 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #1 30 %i.i1 = extractelement <2 x i32> %arg11, i32 0 31 %j.i2 = extractelement <2 x i32> %arg11, i32 1 32 %i.f.i3 = bitcast i32 %i.i1 to float 33 %j.f.i4 = bitcast i32 %j.i2 to float 34 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #1 35 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #1 36 %tmp22.bc = bitcast <32 x i8> %tmp22 to <8 x i32> 37 %tmp24.bc = bitcast <16 x i8> %tmp24 to <4 x i32> 38 %tmp31 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i6, <8 x i32> %tmp22.bc, <4 x i32> %tmp24.bc, i1 0, i32 0, i32 0) 39 40 %tmp32 = extractelement <4 x float> %tmp31, i32 0 41 %tmp33 = extractelement <4 x float> %tmp31, i32 1 42 %tmp34 = extractelement <4 x float> %tmp31, i32 2 43 %tmp35 = extractelement <4 x float> %tmp31, i32 3 44 %tmp36 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp32, float %tmp33) 45 %tmp38 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp34, float %tmp35) 46 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp36, <2 x half> %tmp38, i1 true, i1 false) #0 47 ret void 48} 49 50declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1 51declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1 52declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0 53declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 54declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 55 56attributes #0 = { nounwind } 57attributes #1 = { nounwind readnone } 58attributes #2 = { nounwind readonly } 59 60!0 = !{!1, !1, i64 0, i32 1} 61!1 = !{!"const", !2} 62!2 = !{!"tbaa root"} 63 64 65; CHECK-LABEL: amdgpu_ps_main: 66; CHECK: s_buffer_load_dword 67define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr { 68.entry: 69 %tmp = insertelement <2 x i32> zeroinitializer, i32 %arg, i32 0 70 %tmp1 = bitcast <2 x i32> %tmp to i64 71 %tmp2 = inttoptr i64 %tmp1 to ptr addrspace(4) 72 %tmp3 = load <4 x i32>, ptr addrspace(4) %tmp2, align 16 73 %tmp4 = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp3, i32 0, i32 0) #0 74 switch i32 %tmp4, label %bb [ 75 i32 0, label %bb5 76 i32 1, label %bb6 77 ] 78 79bb: ; preds = %.entry 80 unreachable 81 82bb5: ; preds = %.entry 83 unreachable 84 85bb6: ; preds = %.entry 86 unreachable 87} 88 89; Function Attrs: nounwind readnone 90declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) #1 91