xref: /llvm-project/llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir (revision 042104985cc37d28db5f22f8bdf582c1108977d8)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -run-pass=si-shrink-instructions %s -o - | FileCheck %s
3# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -passes=si-shrink-instructions %s -o - | FileCheck %s
4
5# Make sure flags are preserved when shrinking instructions
6---
7
8name:            shrink_fadd_f32_flags
9tracksRegLiveness: true
10body:             |
11  bb.0:
12    liveins: $vgpr0, $vgpr1
13
14    ; CHECK-LABEL: name: shrink_fadd_f32_flags
15    ; CHECK: liveins: $vgpr0, $vgpr1
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; CHECK-NEXT: [[V_ADD_F32_e32_:%[0-9]+]]:vgpr_32 = nnan nofpexcept V_ADD_F32_e32 [[COPY]], [[COPY1]], implicit $mode, implicit $exec
20    ; CHECK-NEXT: S_NOP 0
21    %0:vgpr_32 = COPY $vgpr0
22    %1:vgpr_32 = COPY $vgpr0
23    %2:vgpr_32 = nofpexcept nnan V_ADD_F32_e64 0, %0, 0, %1, 0, 0, implicit $mode, implicit $exec
24    S_NOP 0
25
26...
27