xref: /llvm-project/llvm/test/CodeGen/AMDGPU/shl_or.ll (revision 5cae88164e5247d01f6a814cf610fa667c9aa9a6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
5; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
6
7; ===================================================================================
8; V_LSHL_OR_B32
9; ===================================================================================
10
11define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) {
12; VI-LABEL: shl_or:
13; VI:       ; %bb.0:
14; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
15; VI-NEXT:    v_or_b32_e32 v0, v0, v2
16; VI-NEXT:    ; return to shader part epilog
17;
18; GFX9-LABEL: shl_or:
19; GFX9:       ; %bb.0:
20; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
21; GFX9-NEXT:    ; return to shader part epilog
22;
23; GFX10-LABEL: shl_or:
24; GFX10:       ; %bb.0:
25; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
26; GFX10-NEXT:    ; return to shader part epilog
27  %x = shl i32 %a, %b
28  %result = or i32 %x, %c
29  %bc = bitcast i32 %result to float
30  ret float %bc
31}
32
33define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
34; VI-LABEL: shl_or_vgpr_c:
35; VI:       ; %bb.0:
36; VI-NEXT:    s_lshl_b32 s0, s2, s3
37; VI-NEXT:    v_or_b32_e32 v0, s0, v0
38; VI-NEXT:    ; return to shader part epilog
39;
40; GFX9-LABEL: shl_or_vgpr_c:
41; GFX9:       ; %bb.0:
42; GFX9-NEXT:    s_lshl_b32 s0, s2, s3
43; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
44; GFX9-NEXT:    ; return to shader part epilog
45;
46; GFX10-LABEL: shl_or_vgpr_c:
47; GFX10:       ; %bb.0:
48; GFX10-NEXT:    v_lshl_or_b32 v0, s2, s3, v0
49; GFX10-NEXT:    ; return to shader part epilog
50  %x = shl i32 %a, %b
51  %result = or i32 %x, %c
52  %bc = bitcast i32 %result to float
53  ret float %bc
54}
55
56define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
57; VI-LABEL: shl_or_vgpr_all2:
58; VI:       ; %bb.0:
59; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
60; VI-NEXT:    v_or_b32_e32 v0, v2, v0
61; VI-NEXT:    ; return to shader part epilog
62;
63; GFX9-LABEL: shl_or_vgpr_all2:
64; GFX9:       ; %bb.0:
65; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
66; GFX9-NEXT:    ; return to shader part epilog
67;
68; GFX10-LABEL: shl_or_vgpr_all2:
69; GFX10:       ; %bb.0:
70; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
71; GFX10-NEXT:    ; return to shader part epilog
72  %x = shl i32 %a, %b
73  %result = or i32 %c, %x
74  %bc = bitcast i32 %result to float
75  ret float %bc
76}
77
78define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
79; VI-LABEL: shl_or_vgpr_ac:
80; VI:       ; %bb.0:
81; VI-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
82; VI-NEXT:    v_or_b32_e32 v0, v0, v1
83; VI-NEXT:    ; return to shader part epilog
84;
85; GFX9-LABEL: shl_or_vgpr_ac:
86; GFX9:       ; %bb.0:
87; GFX9-NEXT:    v_lshl_or_b32 v0, v0, s2, v1
88; GFX9-NEXT:    ; return to shader part epilog
89;
90; GFX10-LABEL: shl_or_vgpr_ac:
91; GFX10:       ; %bb.0:
92; GFX10-NEXT:    v_lshl_or_b32 v0, v0, s2, v1
93; GFX10-NEXT:    ; return to shader part epilog
94  %x = shl i32 %a, %b
95  %result = or i32 %x, %c
96  %bc = bitcast i32 %result to float
97  ret float %bc
98}
99
100define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
101; VI-LABEL: shl_or_vgpr_const:
102; VI:       ; %bb.0:
103; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
104; VI-NEXT:    v_or_b32_e32 v0, 6, v0
105; VI-NEXT:    ; return to shader part epilog
106;
107; GFX9-LABEL: shl_or_vgpr_const:
108; GFX9:       ; %bb.0:
109; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, 6
110; GFX9-NEXT:    ; return to shader part epilog
111;
112; GFX10-LABEL: shl_or_vgpr_const:
113; GFX10:       ; %bb.0:
114; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, 6
115; GFX10-NEXT:    ; return to shader part epilog
116  %x = shl i32 %a, %b
117  %result = or i32 %x, 6
118  %bc = bitcast i32 %result to float
119  ret float %bc
120}
121
122define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) {
123; VI-LABEL: shl_or_vgpr_const2:
124; VI:       ; %bb.0:
125; VI-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
126; VI-NEXT:    v_or_b32_e32 v0, v0, v1
127; VI-NEXT:    ; return to shader part epilog
128;
129; GFX9-LABEL: shl_or_vgpr_const2:
130; GFX9:       ; %bb.0:
131; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 6, v1
132; GFX9-NEXT:    ; return to shader part epilog
133;
134; GFX10-LABEL: shl_or_vgpr_const2:
135; GFX10:       ; %bb.0:
136; GFX10-NEXT:    v_lshl_or_b32 v0, v0, 6, v1
137; GFX10-NEXT:    ; return to shader part epilog
138  %x = shl i32 %a, 6
139  %result = or i32 %x, %b
140  %bc = bitcast i32 %result to float
141  ret float %bc
142}
143
144define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) {
145; VI-LABEL: shl_or_vgpr_const_scalar1:
146; VI:       ; %bb.0:
147; VI-NEXT:    s_lshl_b32 s0, s2, 6
148; VI-NEXT:    v_or_b32_e32 v0, s0, v0
149; VI-NEXT:    ; return to shader part epilog
150;
151; GFX9-LABEL: shl_or_vgpr_const_scalar1:
152; GFX9:       ; %bb.0:
153; GFX9-NEXT:    v_lshl_or_b32 v0, s2, 6, v0
154; GFX9-NEXT:    ; return to shader part epilog
155;
156; GFX10-LABEL: shl_or_vgpr_const_scalar1:
157; GFX10:       ; %bb.0:
158; GFX10-NEXT:    v_lshl_or_b32 v0, s2, 6, v0
159; GFX10-NEXT:    ; return to shader part epilog
160  %x = shl i32 %a, 6
161  %result = or i32 %x, %b
162  %bc = bitcast i32 %result to float
163  ret float %bc
164}
165
166define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) {
167; VI-LABEL: shl_or_vgpr_const_scalar2:
168; VI:       ; %bb.0:
169; VI-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
170; VI-NEXT:    v_or_b32_e32 v0, s2, v0
171; VI-NEXT:    ; return to shader part epilog
172;
173; GFX9-LABEL: shl_or_vgpr_const_scalar2:
174; GFX9:       ; %bb.0:
175; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 6, s2
176; GFX9-NEXT:    ; return to shader part epilog
177;
178; GFX10-LABEL: shl_or_vgpr_const_scalar2:
179; GFX10:       ; %bb.0:
180; GFX10-NEXT:    v_lshl_or_b32 v0, v0, 6, s2
181; GFX10-NEXT:    ; return to shader part epilog
182  %x = shl i32 %a, 6
183  %result = or i32 %x, %b
184  %bc = bitcast i32 %result to float
185  ret float %bc
186}
187