1; REQUIRES: asserts 2 3; RUN: llc -verify-machineinstrs=0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT %s 4; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=greedy -wwm-regalloc=greedy -vgpr-regalloc=greedy -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT %s 5 6; RUN: llc -verify-machineinstrs=0 -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=O0 %s 7 8; RUN: llc -verify-machineinstrs=0 -wwm-regalloc=basic -vgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT-BASIC %s 9; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=BASIC-DEFAULT %s 10; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=basic -wwm-regalloc=basic -vgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=BASIC-BASIC %s 11 12; RUN: not --crash llc -verify-machineinstrs=0 -regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s 13; RUN: not --crash llc -verify-machineinstrs=0 -regalloc=fast -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s 14 15 16; REGALLOC: -regalloc not supported with amdgcn. Use -sgpr-regalloc, -wwm-regalloc, and -vgpr-regalloc 17 18; DEFAULT: Greedy Register Allocator 19; DEFAULT-NEXT: Virtual Register Rewriter 20; DEFAULT-NEXT: Stack Slot Coloring 21; DEFAULT-NEXT: SI lower SGPR spill instructions 22; DEFAULT-NEXT: Virtual Register Map 23; DEFAULT-NEXT: Live Register Matrix 24; DEFAULT-NEXT: SI Pre-allocate WWM Registers 25; DEFAULT-NEXT: Live Stack Slot Analysis 26; DEFAULT-NEXT: Greedy Register Allocator 27; DEFAULT-NEXT: SI Lower WWM Copies 28; DEFAULT-NEXT: Virtual Register Rewriter 29; DEFAULT-NEXT: AMDGPU Reserve WWM Registers 30; DEFAULT-NEXT: Virtual Register Map 31; DEFAULT-NEXT: Live Register Matrix 32; DEFAULT-NEXT: Greedy Register Allocator 33; DEFAULT-NEXT: GCN NSA Reassign 34; DEFAULT-NEXT: Virtual Register Rewriter 35; DEFAULT-NEXT: AMDGPU Mark Last Scratch Load 36; DEFAULT-NEXT: Stack Slot Coloring 37 38; O0: Fast Register Allocator 39; O0-NEXT: SI lower SGPR spill instructions 40; O0-NEXT: Slot index numbering 41; O0-NEXT: Live Interval Analysis 42; O0-NEXT: Virtual Register Map 43; O0-NEXT: Live Register Matrix 44; O0-NEXT: SI Pre-allocate WWM Registers 45; O0-NEXT: Fast Register Allocator 46; O0-NEXT: SI Lower WWM Copies 47; O0-NEXT: AMDGPU Reserve WWM Registers 48; O0-NEXT: Fast Register Allocator 49; O0-NEXT: SI Fix VGPR copies 50 51 52 53 54; BASIC-DEFAULT: Debug Variable Analysis 55; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis 56; BASIC-DEFAULT-NEXT: Machine Natural Loop Construction 57; BASIC-DEFAULT-NEXT: Machine Block Frequency Analysis 58; BASIC-DEFAULT-NEXT: Virtual Register Map 59; BASIC-DEFAULT-NEXT: Live Register Matrix 60; BASIC-DEFAULT-NEXT: Basic Register Allocator 61; BASIC-DEFAULT-NEXT: Virtual Register Rewriter 62; BASIC-DEFAULT-NEXT: Stack Slot Coloring 63; BASIC-DEFAULT-NEXT: SI lower SGPR spill instructions 64; BASIC-DEFAULT-NEXT: Virtual Register Map 65; BASIC-DEFAULT-NEXT: Live Register Matrix 66; BASIC-DEFAULT-NEXT: SI Pre-allocate WWM Registers 67; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis 68; BASIC-DEFAULT-NEXT: Bundle Machine CFG Edges 69; BASIC-DEFAULT-NEXT: Spill Code Placement Analysis 70; BASIC-DEFAULT-NEXT: Lazy Machine Block Frequency Analysis 71; BASIC-DEFAULT-NEXT: Machine Optimization Remark Emitter 72; BASIC-DEFAULT-NEXT: Greedy Register Allocator 73; BASIC-DEFAULT-NEXT: SI Lower WWM Copies 74; BASIC-DEFAULT-NEXT: Virtual Register Rewriter 75; BASIC-DEFAULT-NEXT: AMDGPU Reserve WWM Registers 76; BASIC-DEFAULT-NEXT: Virtual Register Map 77; BASIC-DEFAULT-NEXT: Live Register Matrix 78; BASIC-DEFAULT-NEXT: Greedy Register Allocator 79; BASIC-DEFAULT-NEXT: GCN NSA Reassign 80; BASIC-DEFAULT-NEXT: Virtual Register Rewriter 81; BASIC-DEFAULT-NEXT: AMDGPU Mark Last Scratch Load 82; BASIC-DEFAULT-NEXT: Stack Slot Coloring 83 84 85 86; DEFAULT-BASIC: Greedy Register Allocator 87; DEFAULT-BASIC-NEXT: Virtual Register Rewriter 88; DEFAULT-BASIC-NEXT: Stack Slot Coloring 89; DEFAULT-BASIC-NEXT: SI lower SGPR spill instructions 90; DEFAULT-BASIC-NEXT: Virtual Register Map 91; DEFAULT-BASIC-NEXT: Live Register Matrix 92; DEFAULT-BASIC-NEXT: SI Pre-allocate WWM Registers 93; DEFAULT-BASIC-NEXT: Live Stack Slot Analysis 94; DEFAULT-BASIC-NEXT: Basic Register Allocator 95; DEFAULT-BASIC-NEXT: SI Lower WWM Copies 96; DEFAULT-BASIC-NEXT: Virtual Register Rewriter 97; DEFAULT-BASIC-NEXT: AMDGPU Reserve WWM Registers 98; DEFAULT-BASIC-NEXT: Virtual Register Map 99; DEFAULT-BASIC-NEXT: Live Register Matrix 100; DEFAULT-BASIC-NEXT: Basic Register Allocator 101; DEFAULT-BASIC-NEXT: GCN NSA Reassign 102; DEFAULT-BASIC-NEXT: Virtual Register Rewriter 103; DEFAULT-BASIC-NEXT: AMDGPU Mark Last Scratch Load 104; DEFAULT-BASIC-NEXT: Stack Slot Coloring 105 106 107 108; BASIC-BASIC: Debug Variable Analysis 109; BASIC-BASIC-NEXT: Live Stack Slot Analysis 110; BASIC-BASIC-NEXT: Machine Natural Loop Construction 111; BASIC-BASIC-NEXT: Machine Block Frequency Analysis 112; BASIC-BASIC-NEXT: Virtual Register Map 113; BASIC-BASIC-NEXT: Live Register Matrix 114; BASIC-BASIC-NEXT: Basic Register Allocator 115; BASIC-BASIC-NEXT: Virtual Register Rewriter 116; BASIC-BASIC-NEXT: Stack Slot Coloring 117; BASIC-BASIC-NEXT: SI lower SGPR spill instructions 118; BASIC-BASIC-NEXT: Virtual Register Map 119; BASIC-BASIC-NEXT: Live Register Matrix 120; BASIC-BASIC-NEXT: SI Pre-allocate WWM Registers 121; BASIC-BASIC-NEXT: Live Stack Slot Analysis 122; BASIC-BASIC-NEXT: Basic Register Allocator 123; BASIC-BASIC-NEXT: SI Lower WWM Copies 124; BASIC-BASIC-NEXT: Virtual Register Rewriter 125; BASIC-BASIC-NEXT: AMDGPU Reserve WWM Registers 126; BASIC-BASIC-NEXT: Virtual Register Map 127; BASIC-BASIC-NEXT: Live Register Matrix 128; BASIC-BASIC-NEXT: Basic Register Allocator 129; BASIC-BASIC-NEXT: GCN NSA Reassign 130; BASIC-BASIC-NEXT: Virtual Register Rewriter 131; BASIC-BASIC-NEXT: AMDGPU Mark Last Scratch Load 132; BASIC-BASIC-NEXT: Stack Slot Coloring 133 134 135declare void @bar() 136 137; Something with some CSR SGPR spills 138define void @foo() { 139 call void asm sideeffect "; clobber", "~{s33}"() 140 call void @bar() 141 ret void 142} 143 144; Block live out spills with fast regalloc 145define amdgpu_kernel void @control_flow(i1 %cond) { 146 %s33 = call i32 asm sideeffect "; clobber", "={s33}"() 147 br i1 %cond, label %bb0, label %bb1 148 149bb0: 150 call void asm sideeffect "; use %0", "s"(i32 %s33) 151 br label %bb1 152 153bb1: 154 ret void 155} 156