1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s 3 4; CHECK-LABEL: {{^}}phi1: 5; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 6; CHECK: ; %bb.1: ; %ELSE 7; CHECK: s_xor_b32 s{{[0-9]}}, [[DST]] 8define amdgpu_ps void @phi1(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 9main_body: 10 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 11 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0) 12 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0) 13 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0) 14 %tmp24 = fptosi float %tmp22 to i32 15 %tmp25 = icmp ne i32 %tmp24, 0 16 br i1 %tmp25, label %ENDIF, label %ELSE 17 18ELSE: ; preds = %main_body 19 %tmp26 = fsub float -0.000000e+00, %tmp21 20 br label %ENDIF 21 22ENDIF: ; preds = %ELSE, %main_body 23 %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ] 24 %tmp27 = fadd float %temp.0, %tmp23 25 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0 26 ret void 27} 28 29; Make sure this program doesn't crash 30; CHECK-LABEL: {{^}}phi2: 31define amdgpu_ps void @phi2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 { 32main_body: 33 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 34 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0) 35 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0) 36 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 36, i32 0) 37 %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 40, i32 0) 38 %tmp25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 48, i32 0) 39 %tmp26 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 52, i32 0) 40 %tmp27 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 56, i32 0) 41 %tmp28 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 64, i32 0) 42 %tmp29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 68, i32 0) 43 %tmp30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 72, i32 0) 44 %tmp31 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 76, i32 0) 45 %tmp32 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 80, i32 0) 46 %tmp33 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 84, i32 0) 47 %tmp34 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 88, i32 0) 48 %tmp35 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 92, i32 0) 49 %tmp37 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0 50 %tmp39 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0 51 %i.i = extractelement <2 x i32> %arg5, i32 0 52 %j.i = extractelement <2 x i32> %arg5, i32 1 53 %i.f.i = bitcast i32 %i.i to float 54 %j.f.i = bitcast i32 %j.i to float 55 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #1 56 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #1 57 %i.i19 = extractelement <2 x i32> %arg5, i32 0 58 %j.i20 = extractelement <2 x i32> %arg5, i32 1 59 %i.f.i21 = bitcast i32 %i.i19 to float 60 %j.f.i22 = bitcast i32 %j.i20 to float 61 %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 1, i32 0, i32 %arg3) #1 62 %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 1, i32 0, i32 %arg3) #1 63 %i.i13 = extractelement <2 x i32> %arg5, i32 0 64 %j.i14 = extractelement <2 x i32> %arg5, i32 1 65 %i.f.i15 = bitcast i32 %i.i13 to float 66 %j.f.i16 = bitcast i32 %j.i14 to float 67 %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 1, i32 %arg3) #1 68 %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 1, i32 %arg3) #1 69 %i.i7 = extractelement <2 x i32> %arg5, i32 0 70 %j.i8 = extractelement <2 x i32> %arg5, i32 1 71 %i.f.i9 = bitcast i32 %i.i7 to float 72 %j.f.i10 = bitcast i32 %j.i8 to float 73 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 1, i32 %arg3) #1 74 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 1, i32 %arg3) #1 75 %i.i1 = extractelement <2 x i32> %arg5, i32 0 76 %j.i2 = extractelement <2 x i32> %arg5, i32 1 77 %i.f.i3 = bitcast i32 %i.i1 to float 78 %j.f.i4 = bitcast i32 %j.i2 to float 79 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 1, i32 %arg3) #1 80 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 1, i32 %arg3) #1 81 %tmp39.bc = bitcast <4 x i32> %tmp39 to <4 x i32> 82 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i24, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i1 0, i32 0, i32 0) 83 %tmp50 = extractelement <4 x float> %tmp1, i32 2 84 %tmp51 = call float @llvm.fabs.f32(float %tmp50) 85 %tmp52 = fmul float %p2.i18, %p2.i18 86 %tmp53 = fmul float %p2.i12, %p2.i12 87 %tmp54 = fadd float %tmp53, %tmp52 88 %tmp55 = fmul float %p2.i6, %p2.i6 89 %tmp56 = fadd float %tmp54, %tmp55 90 %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56) 91 %tmp58 = fmul float %p2.i18, %tmp57 92 %tmp59 = fmul float %p2.i12, %tmp57 93 %tmp60 = fmul float %p2.i6, %tmp57 94 %tmp61 = fmul float %tmp58, %tmp22 95 %tmp62 = fmul float %tmp59, %tmp23 96 %tmp63 = fadd float %tmp62, %tmp61 97 %tmp64 = fmul float %tmp60, %tmp24 98 %tmp65 = fadd float %tmp63, %tmp64 99 %tmp66 = fsub float -0.000000e+00, %tmp25 100 %tmp67 = fmul float %tmp65, %tmp51 101 %tmp68 = fadd float %tmp67, %tmp66 102 %tmp69 = fmul float %tmp26, %tmp68 103 %tmp70 = fmul float %tmp27, %tmp68 104 %tmp71 = call float @llvm.fabs.f32(float %tmp69) 105 %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71 106 %tmp73 = sext i1 %tmp72 to i32 107 %tmp74 = bitcast i32 %tmp73 to float 108 %tmp75 = bitcast float %tmp74 to i32 109 %tmp76 = icmp ne i32 %tmp75, 0 110 br i1 %tmp76, label %IF, label %ENDIF 111 112IF: ; preds = %main_body 113 %tmp77 = fsub float -0.000000e+00, %tmp69 114 %tmp78 = call float @llvm.exp2.f32(float %tmp77) 115 %tmp79 = fsub float -0.000000e+00, %tmp78 116 %tmp80 = fadd float 1.000000e+00, %tmp79 117 %tmp81 = fdiv float 1.000000e+00, %tmp69 118 %tmp82 = fmul float %tmp80, %tmp81 119 %tmp83 = fmul float %tmp31, %tmp82 120 br label %ENDIF 121 122ENDIF: ; preds = %IF, %main_body 123 %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ] 124 %tmp84 = call float @llvm.fabs.f32(float %tmp70) 125 %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84 126 %tmp86 = sext i1 %tmp85 to i32 127 %tmp87 = bitcast i32 %tmp86 to float 128 %tmp88 = bitcast float %tmp87 to i32 129 %tmp89 = icmp ne i32 %tmp88, 0 130 br i1 %tmp89, label %IF25, label %ENDIF24 131 132IF25: ; preds = %ENDIF 133 %tmp90 = fsub float -0.000000e+00, %tmp70 134 %tmp91 = call float @llvm.exp2.f32(float %tmp90) 135 %tmp92 = fsub float -0.000000e+00, %tmp91 136 %tmp93 = fadd float 1.000000e+00, %tmp92 137 %tmp94 = fdiv float 1.000000e+00, %tmp70 138 %tmp95 = fmul float %tmp93, %tmp94 139 %tmp96 = fmul float %tmp35, %tmp95 140 br label %ENDIF24 141 142ENDIF24: ; preds = %IF25, %ENDIF 143 %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ] 144 %tmp97 = fmul float %tmp28, %temp4.0 145 %tmp98 = fmul float %tmp29, %temp4.0 146 %tmp99 = fmul float %tmp30, %temp4.0 147 %tmp100 = fmul float %tmp32, %temp8.0 148 %tmp101 = fadd float %tmp100, %tmp97 149 %tmp102 = fmul float %tmp33, %temp8.0 150 %tmp103 = fadd float %tmp102, %tmp98 151 %tmp104 = fmul float %tmp34, %temp8.0 152 %tmp105 = fadd float %tmp104, %tmp99 153 %tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21) 154 %tmp107 = fsub float -0.000000e+00, %tmp101 155 %tmp108 = fmul float %tmp107, %tmp106 156 %tmp109 = fsub float -0.000000e+00, %tmp103 157 %tmp110 = fmul float %tmp109, %tmp106 158 %tmp111 = fsub float -0.000000e+00, %tmp105 159 %tmp112 = fmul float %tmp111, %tmp106 160 %tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110) 161 %tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00) 162 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0 163 ret void 164} 165 166; We just want to make sure the program doesn't crash 167; CHECK-LABEL: {{^}}loop: 168define amdgpu_ps void @loop(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 169main_body: 170 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 171 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0) 172 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 4, i32 0) 173 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 8, i32 0) 174 %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 12, i32 0) 175 %tmp25 = fptosi float %tmp24 to i32 176 %tmp26 = bitcast i32 %tmp25 to float 177 %tmp27 = bitcast float %tmp26 to i32 178 br label %LOOP 179 180LOOP: ; preds = %ENDIF, %main_body 181 %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ] 182 %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ] 183 %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ] 184 %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ] 185 %tmp28 = bitcast float %temp8.0 to i32 186 %tmp29 = icmp sge i32 %tmp28, %tmp27 187 %tmp30 = sext i1 %tmp29 to i32 188 %tmp31 = bitcast i32 %tmp30 to float 189 %tmp32 = bitcast float %tmp31 to i32 190 %tmp33 = icmp ne i32 %tmp32, 0 191 br i1 %tmp33, label %IF, label %ENDIF 192 193IF: ; preds = %LOOP 194 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00, i1 true, i1 true) #0 195 ret void 196 197ENDIF: ; preds = %LOOP 198 %tmp34 = bitcast float %temp8.0 to i32 199 %tmp35 = add i32 %tmp34, 1 200 %tmp36 = bitcast i32 %tmp35 to float 201 br label %LOOP 202} 203 204; This checks for a bug in the FixSGPRCopies pass where VReg96 205; registers were being identified as an SGPR regclass which was causing 206; an assertion failure. 207 208; CHECK-LABEL: {{^}}sample_v3: 209; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5 210; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7 211; CHECK: s_cbranch 212 213; CHECK: BB{{[0-9]+_[0-9]+}}: 214; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11 215; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13 216 217; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v[[[SAMPLE_LO]]:[[SAMPLE_HI]]] 218; CHECK: exp 219; CHECK: s_endpgm 220define amdgpu_ps void @sample_v3(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 221entry: 222 %tmp21 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0 223 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 16, i32 0) 224 %tmp24 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0 225 %tmp26 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0 226 %tmp27 = fcmp oeq float %tmp22, 0.000000e+00 227 %tmp26.bc = bitcast <4 x i32> %tmp26 to <4 x i32> 228 br i1 %tmp27, label %if, label %else 229 230if: ; preds = %entry 231 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36D6000000000000, float 0x36DA000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0) 232 %val.if.0 = extractelement <4 x float> %tmp1, i32 0 233 %val.if.1 = extractelement <4 x float> %tmp1, i32 1 234 %val.if.2 = extractelement <4 x float> %tmp1, i32 2 235 br label %endif 236 237else: ; preds = %entry 238 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36C4000000000000, float 0x36CC000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0) 239 %val.else.0 = extractelement <4 x float> %tmp2, i32 0 240 %val.else.1 = extractelement <4 x float> %tmp2, i32 1 241 %val.else.2 = extractelement <4 x float> %tmp2, i32 2 242 br label %endif 243 244endif: ; preds = %else, %if 245 %val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ] 246 %val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ] 247 %val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ] 248 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %val.0, float %val.1, float %val.2, float 0.000000e+00, i1 true, i1 true) #0 249 ret void 250} 251 252; CHECK-LABEL: {{^}}copy1: 253; CHECK: buffer_load_dword 254; CHECK: v_add 255; CHECK: s_endpgm 256define amdgpu_kernel void @copy1(ptr addrspace(1) %out, ptr addrspace(1) %in0) { 257entry: 258 %tmp = load float, ptr addrspace(1) %in0 259 %tmp1 = fcmp oeq float %tmp, 0.000000e+00 260 br i1 %tmp1, label %if0, label %endif 261 262if0: ; preds = %entry 263 %tmp2 = bitcast float %tmp to i32 264 %tmp3 = fcmp olt float %tmp, 0.000000e+00 265 br i1 %tmp3, label %if1, label %endif 266 267if1: ; preds = %if0 268 %tmp4 = add i32 %tmp2, 1 269 br label %endif 270 271endif: ; preds = %if1, %if0, %entry 272 %tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ] 273 %tmp6 = bitcast i32 %tmp5 to float 274 store float %tmp6, ptr addrspace(1) %out 275 ret void 276} 277 278; This test is just checking that we don't crash / assertion fail. 279; CHECK-LABEL: {{^}}copy2: 280; CHECK: s_endpgm 281define amdgpu_ps void @copy2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 282entry: 283 br label %LOOP68 284 285LOOP68: ; preds = %ENDIF69, %entry 286 %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ] 287 %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ] 288 %g = icmp eq i32 0, %t 289 %l = bitcast float %temp4.7 to i32 290 br i1 %g, label %IF70, label %ENDIF69 291 292IF70: ; preds = %LOOP68 293 %q = icmp ne i32 %l, 13 294 %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00 295 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0 296 ret void 297 298ENDIF69: ; preds = %LOOP68 299 %u = add i32 %l, %t 300 %v = bitcast i32 %u to float 301 %x = add i32 %t, -1 302 br label %LOOP68 303} 304 305; This test checks that image_sample resource descriptors aren't loaded into 306; vgprs. The verifier will fail if this happens. 307; CHECK-LABEL:{{^}}sample_rsrc 308 309; CHECK: s_cmp_eq_u32 310; CHECK: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]] 311 312; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} 313; CHECK: s_endpgm 314 315; [[END]]: 316; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}} 317; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]] 318; CHECK: s_branch 319define amdgpu_ps void @sample_rsrc(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { 320bb: 321 %tmp22 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !3 322 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp22, i32 16, i32 0) 323 %tmp26 = load <8 x i32>, ptr addrspace(4) %arg3, !tbaa !3 324 %tmp28 = load <4 x i32>, ptr addrspace(4) %arg2, !tbaa !3 325 %i.i = extractelement <2 x i32> %arg7, i32 0 326 %j.i = extractelement <2 x i32> %arg7, i32 1 327 %i.f.i = bitcast i32 %i.i to float 328 %j.f.i = bitcast i32 %j.i to float 329 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0 330 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0 331 %i.i1 = extractelement <2 x i32> %arg7, i32 0 332 %j.i2 = extractelement <2 x i32> %arg7, i32 1 333 %i.f.i3 = bitcast i32 %i.i1 to float 334 %j.f.i4 = bitcast i32 %j.i2 to float 335 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #0 336 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #0 337 %tmp31 = bitcast float %tmp23 to i32 338 %tmp36 = icmp ne i32 %tmp31, 0 339 br i1 %tmp36, label %bb38, label %bb80 340 341bb38: ; preds = %bb 342 %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32> 343 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i6, <8 x i32> %tmp56, <4 x i32> %tmp28, i1 0, i32 0, i32 0) 344 br label %bb71 345 346bb80: ; preds = %bb 347 %tmp81 = bitcast float %p2.i to i32 348 %tmp82 = bitcast float %p2.i6 to i32 349 %tmp82.2 = add i32 %tmp82, 1 350 %tmp83 = bitcast i32 %tmp81 to float 351 %tmp84 = bitcast i32 %tmp82.2 to float 352 %tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32> 353 %tmp3 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp83, float %tmp84, <8 x i32> %tmp85, <4 x i32> %tmp28, i1 0, i32 0, i32 0) 354 br label %bb71 355 356bb71: ; preds = %bb80, %bb38 357 %tmp72 = phi <4 x float> [ %tmp2, %bb38 ], [ %tmp3, %bb80 ] 358 %tmp88 = extractelement <4 x float> %tmp72, i32 0 359 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0 360 ret void 361} 362 363; Check the resource descriptor is stored in an sgpr. 364; CHECK-LABEL: {{^}}mimg_srsrc_sgpr: 365; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 366define amdgpu_ps void @mimg_srsrc_sgpr(ptr addrspace(4) inreg %arg) #0 { 367bb: 368 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 369 %tmp7 = getelementptr [34 x <8 x i32>], ptr addrspace(4) %arg, i32 0, i32 %tid 370 %tmp8 = load <8 x i32>, ptr addrspace(4) %tmp7, align 32, !tbaa !0 371 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> %tmp8, <4 x i32> undef, i1 0, i32 0, i32 0) 372 %tmp10 = extractelement <4 x float> %tmp, i32 0 373 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10) 374 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 375 ret void 376} 377 378; Check the sampler is stored in an sgpr. 379; CHECK-LABEL: {{^}}mimg_ssamp_sgpr: 380; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 381define amdgpu_ps void @mimg_ssamp_sgpr(ptr addrspace(4) inreg %arg) #0 { 382bb: 383 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 384 %tmp7 = getelementptr [17 x <4 x i32>], ptr addrspace(4) %arg, i32 0, i32 %tid 385 %tmp8 = load <4 x i32>, ptr addrspace(4) %tmp7, align 16, !tbaa !0 386 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> undef, <4 x i32> %tmp8, i1 0, i32 0, i32 0) 387 %tmp10 = extractelement <4 x float> %tmp, i32 0 388 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef) 389 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 390 ret void 391} 392 393declare float @llvm.fabs.f32(float) #1 394declare float @llvm.amdgcn.rsq.f32(float) #1 395declare float @llvm.exp2.f32(float) #1 396declare float @llvm.pow.f32(float, float) #1 397declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 398declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1 399declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1 400declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 401declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0 402declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 403declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 404declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1 405 406attributes #0 = { nounwind } 407attributes #1 = { nounwind readnone } 408attributes #2 = { nounwind readonly } 409 410!0 = !{!1, !1, i64 0, i32 1} 411!1 = !{!"const", !2} 412!2 = !{!"tbaa root"} 413!3 = !{!1, !1, i64 0} 414