xref: /llvm-project/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.legal.f16.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI %s
3
4; FIXME: This one should fold to rcp
5define half @select_fneg_posk_src_rcp_f16(i32 %c, half %x, half %y) {
6; VI-LABEL: select_fneg_posk_src_rcp_f16:
7; VI:       ; %bb.0:
8; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9; VI-NEXT:    v_rcp_f16_e64 v1, -v1
10; VI-NEXT:    v_mov_b32_e32 v2, 0x4000
11; VI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
12; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
13; VI-NEXT:    s_setpc_b64 s[30:31]
14  %cmp = icmp eq i32 %c, 0
15  %rcp = call half @llvm.amdgcn.rcp.f16(half %x)
16  %fneg = fneg half %rcp
17  %select = select i1 %cmp, half %fneg, half 2.0
18  ret half %select
19}
20
21declare half @llvm.amdgcn.rcp.f16(half) #0
22
23attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
24