1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s 3 4declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone 5declare i32 @llvm.amdgcn.sffbh.i32(i32) nounwind readnone speculatable 6define amdgpu_kernel void @select_constant_cttz(ptr addrspace(1) noalias %out, ptr addrspace(1) nocapture readonly %arrayidx) nounwind { 7; GCN-LABEL: select_constant_cttz: 8; GCN: ; %bb.0: 9; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 10; GCN-NEXT: s_waitcnt lgkmcnt(0) 11; GCN-NEXT: s_load_dword s2, s[2:3], 0x0 12; GCN-NEXT: s_mov_b32 s3, 0xf000 13; GCN-NEXT: s_waitcnt lgkmcnt(0) 14; GCN-NEXT: s_lshr_b32 s4, 1, s2 15; GCN-NEXT: s_cmp_lg_u32 s2, 0 16; GCN-NEXT: s_ff1_i32_b32 s2, s4 17; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 18; GCN-NEXT: s_and_b64 s[6:7], s[4:5], exec 19; GCN-NEXT: s_cselect_b32 s2, -1, s2 20; GCN-NEXT: s_flbit_i32 s6, s2 21; GCN-NEXT: s_sub_i32 s8, 31, s6 22; GCN-NEXT: s_cmp_eq_u32 s2, 0 23; GCN-NEXT: s_cselect_b64 s[6:7], -1, 0 24; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] 25; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec 26; GCN-NEXT: s_cselect_b32 s4, -1, s8 27; GCN-NEXT: s_mov_b32 s2, -1 28; GCN-NEXT: v_mov_b32_e32 v0, s4 29; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 30; GCN-NEXT: s_endpgm 31 %v = load i32, ptr addrspace(1) %arrayidx, align 4 32 %sr = lshr i32 1, %v 33 %cmp = icmp ne i32 %v, 0 34 %cttz = call i32 @llvm.cttz.i32(i32 %sr, i1 true), !range !0 35 %sel = select i1 %cmp, i32 -1, i32 %cttz 36 %ffbh = call i32 @llvm.amdgcn.sffbh.i32(i32 %sel) 37 %sub = sub i32 31, %ffbh 38 %cmp2 = icmp eq i32 %sel, 0 39 %or = or i1 %cmp, %cmp2 40 %sel2 = select i1 %or, i32 -1, i32 %sub 41 store i32 %sel2, ptr addrspace(1) %out 42 ret void 43} 44 45!0 = !{i32 0, i32 33} 46