1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -o - < %s | FileCheck -check-prefix=CHECK %s 3 4; The si-peephole-sdwa pass has mishandled the selections of preexisting sdwa instructions 5; which led to an instruction of this shape: 6; v_lshlrev_b32_sdwa v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 7; instead of 8; v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 9 10define amdgpu_kernel void @widget(ptr addrspace(1) %arg, i1 %arg1, ptr addrspace(3) %arg2, ptr addrspace(3) %arg3) { 11; CHECK-LABEL: widget: 12; CHECK: ; %bb.0: ; %bb 13; CHECK-NEXT: s_clause 0x1 14; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 15; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8 16; CHECK-NEXT: v_mov_b32_e32 v2, 8 17; CHECK-NEXT: s_waitcnt lgkmcnt(0) 18; CHECK-NEXT: s_clause 0x1 19; CHECK-NEXT: global_load_ushort v1, v0, s[0:1] 20; CHECK-NEXT: global_load_ubyte v0, v0, s[0:1] offset:2 21; CHECK-NEXT: s_bitcmp1_b32 s2, 0 22; CHECK-NEXT: s_cselect_b32 s0, -1, 0 23; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s0 24; CHECK-NEXT: s_waitcnt vmcnt(1) 25; CHECK-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD 26; CHECK-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 27; CHECK-NEXT: v_and_b32_e32 v1, 0xffff, v1 28; CHECK-NEXT: s_waitcnt vmcnt(0) 29; CHECK-NEXT: v_lshl_or_b32 v0, v0, 16, v1 30; CHECK-NEXT: s_cbranch_vccz .LBB0_2 31; CHECK-NEXT: ; %bb.1: ; %bb19 32; CHECK-NEXT: v_mov_b32_e32 v1, 0 33; CHECK-NEXT: ds_write_b32 v1, v1 34; CHECK-NEXT: .LBB0_2: ; %bb20 35; CHECK-NEXT: v_lshrrev_b32_e32 v0, 16, v0 36; CHECK-NEXT: s_mov_b32 s0, exec_lo 37; CHECK-NEXT: v_cmpx_ne_u16_e32 0, v0 38; CHECK-NEXT: s_xor_b32 s0, exec_lo, s0 39; CHECK-NEXT: s_cbranch_execz .LBB0_4 40; CHECK-NEXT: ; %bb.3: ; %bb11 41; CHECK-NEXT: v_mov_b32_e32 v1, 2 42; CHECK-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 43; CHECK-NEXT: v_mov_b32_e32 v1, 0 44; CHECK-NEXT: ds_write_b32 v0, v1 offset:84 45; CHECK-NEXT: .LBB0_4: ; %bb14 46; CHECK-NEXT: s_endpgm 47bb: 48 %call = tail call i32 @llvm.amdgcn.workitem.id.x() 49 %zext = zext i32 %call to i64 50 %getelementptr = getelementptr i8, ptr addrspace(1) %arg, i64 %zext 51 %load = load i8, ptr addrspace(1) %getelementptr, align 1 52 %or = or disjoint i32 %call, 1 53 %zext4 = zext i32 %or to i64 54 %getelementptr5 = getelementptr i8, ptr addrspace(1) %arg, i64 %zext4 55 %load6 = load i8, ptr addrspace(1) %getelementptr5, align 1 56 %or7 = or disjoint i32 %call, 2 57 %zext8 = zext i32 %or7 to i64 58 %getelementptr9 = getelementptr i8, ptr addrspace(1) %arg, i64 %zext8 59 %load10 = load i8, ptr addrspace(1) %getelementptr9, align 1 60 br i1 %arg1, label %bb19, label %bb20 61 62bb11: ; preds = %bb20 63 %zext12 = zext i8 %load10 to i64 64 %getelementptr13 = getelementptr nusw [14 x i32], ptr addrspace(3) inttoptr (i32 84 to ptr addrspace(3)), i64 0, i64 %zext12 65 store i32 0, ptr addrspace(3) %getelementptr13, align 4 66 br label %bb14 67 68bb14: ; preds = %bb20, %bb11 69 %zext15 = zext i8 %load6 to i64 70 %getelementptr16 = getelementptr [14 x i32], ptr addrspace(3) %arg2, i64 0, i64 %zext15 71 %zext17 = zext i8 %load to i64 72 %getelementptr18 = getelementptr [14 x i32], ptr addrspace(3) %arg3, i64 0, i64 %zext17 73 ret void 74 75bb19: ; preds = %bb 76 store i32 0, ptr addrspace(3) null, align 4 77 br label %bb20 78 79bb20: ; preds = %bb19, %bb 80 %icmp = icmp eq i8 %load10, 0 81 br i1 %icmp, label %bb14, label %bb11 82} 83 84; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) 85declare noundef i32 @llvm.amdgcn.workitem.id.x() #0 86 87attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 88