xref: /llvm-project/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1# RUN: llc -mtriple=amdgcn -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
2# RUN: llc -mtriple=amdgcn -misched-regpressure=false -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=NORP
3
4# REQUIRES: asserts
5
6# Check there is no SReg_32 pressure created by DS_* instructions because of M0 use
7
8# CHECK: ScheduleDAGMILive::schedule starting
9# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} implicit $m0, implicit $exec
10# CHECK: Pressure Diff : {{$}}
11# CHECK: SU({{.*}} DS_WRITE_B32
12
13# NORP: ScheduleDAGMILive::schedule starting
14# NORP: GenericScheduler RegionPolicy:  ShouldTrackPressure=0
15# NORP-NOT: Pressure Diff : {{$}}
16# NORP-NOT: Pressure Diff : {{$}}
17# NORP-NOT: Pressure Diff : {{$}}
18# NORP-NOT: Pressure Diff : {{$}}
19# NORP-NOT: Pressure Diff : {{$}}
20# NORP-NOT: Pressure Diff : {{$}}
21# NORP-NOT: Bottom Pressure:
22# NORP-NOT: UpdateRegP
23# NORP-NOT: UpdateRegP
24# NORP-NOT: UpdateRegP
25
26---
27name:            mo_pset
28alignment:       1
29exposesReturnsTwice: false
30legalized:       false
31regBankSelected: false
32selected:        false
33tracksRegLiveness: true
34registers:
35  - { id: 0, class: sgpr_128 }
36  - { id: 1, class: sgpr_64 }
37  - { id: 2, class: sreg_32_xm0 }
38  - { id: 3, class: sgpr_32 }
39  - { id: 4, class: vgpr_32 }
40  - { id: 5, class: sreg_32_xm0_xexec }
41  - { id: 6, class: vgpr_32 }
42  - { id: 7, class: vgpr_32 }
43  - { id: 8, class: vgpr_32 }
44liveins:
45  - { reg: '$sgpr4_sgpr5', virtual-reg: '%1' }
46frameInfo:
47  isFrameAddressTaken: false
48  isReturnAddressTaken: false
49  hasStackMap:     false
50  hasPatchPoint:   false
51  stackSize:       0
52  offsetAdjustment: 0
53  maxAlignment:    0
54  adjustsStack:    false
55  hasCalls:        false
56  maxCallFrameSize: 0
57  hasOpaqueSPAdjustment: false
58  hasVAStart:      false
59  hasMustTailInVarArgFunc: false
60body:             |
61  bb.0:
62    liveins: $sgpr4_sgpr5
63
64    %1 = COPY $sgpr4_sgpr5
65    %5 = S_LOAD_DWORD_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load (s32) from `ptr addrspace(4) undef`)
66    $m0 = S_MOV_B32 -1
67    %7 = COPY %5
68    %6 = DS_READ_B32 %7, 0, 0, implicit $m0, implicit $exec
69    DS_WRITE_B32 %7, %6, 4, 0, implicit killed $m0, implicit $exec
70    S_ENDPGM 0
71
72...
73