xref: /llvm-project/llvm/test/CodeGen/AMDGPU/sched-setprio.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
2
3declare void @llvm.amdgcn.s.setprio(i16)
4declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32)
5
6; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32:
7; GCN: s_setprio 1
8; GCN: v_mfma
9; GCN: v_mfma
10; GCN: s_setprio 0
11define amdgpu_kernel void @test_mfma_f32_4x4x1f32(ptr addrspace(1) %arg) #0 {
12bb:
13  %in.1 = load <4 x float>, ptr addrspace(1) %arg
14  call void @llvm.amdgcn.s.setprio(i16 1)
15  %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 2.0, <4 x float> %in.1, i32 0, i32 0, i32 0)
16  %mai.2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 3.0, float 4.0, <4 x float> %mai.1, i32 0, i32 0, i32 0)
17  call void @llvm.amdgcn.s.setprio(i16 0)
18  store <4 x float> %mai.2, ptr addrspace(1) %arg
19  ret void
20}
21