xref: /llvm-project/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir (revision e7900e695e7dfb36be8651d914a31f42a5d6c634) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
3
4# The sequence of DBG_VALUEs forms a scheduling region with 0 real
5# instructions. The RegPressure tracker would end up skipping over any
6# debug instructions, so it would point to the instruction
7# before/outside of the region, hitting this assert:
8#  assert((BotRPTracker.getPos() == RegionEnd ||
9#          (RegionEnd->isDebugInstr() &&
10#           BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
11#         "Can't find the region bottom");
12
13---
14name:            only_dbg_value_sched_region
15tracksRegLiveness: true
16machineFunctionInfo:
17  isEntryFunction: true
18  waveLimiter:     true
19body:             |
20  ; CHECK-LABEL: name: only_dbg_value_sched_region
21  ; CHECK: bb.0:
22  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
23  ; CHECK-NEXT:   liveins: $vgpr0
24  ; CHECK-NEXT: {{  $}}
25  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
26  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
27  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec
28  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, implicit $exec
29  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]
30  ; CHECK-NEXT:   undef [[V_ADD_F32_e32_:%[0-9]+]].sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $mode, implicit $exec
31  ; CHECK-NEXT:   dead undef [[V_ADD_F32_e32_:%[0-9]+]].sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $mode, implicit $exec
32  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, implicit $exec
33  ; CHECK-NEXT:   undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
34  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
35  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec
36  ; CHECK-NEXT:   undef [[V_ADD_F32_e32_1:%[0-9]+]].sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $mode, implicit $exec
37  ; CHECK-NEXT:   [[V_ADD_F32_e32_1:%[0-9]+]].sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $mode, implicit $exec
38  ; CHECK-NEXT:   GLOBAL_STORE_DWORDX2 [[V_ADD_F32_e32_1]], [[V_MOV_B32_e32_]], 32, 0, implicit $exec
39  ; CHECK-NEXT:   undef [[GLOBAL_LOAD_DWORD2:%[0-9]+]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, implicit $exec
40  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
41  ; CHECK-NEXT:   [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
42  ; CHECK-NEXT:   [[DEF2:%[0-9]+]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, implicit $exec
43  ; CHECK-NEXT:   [[GLOBAL_LOAD_DWORD2:%[0-9]+]].sub1:vreg_64 = IMPLICIT_DEF
44  ; CHECK-NEXT:   [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
45  ; CHECK-NEXT:   [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
46  ; CHECK-NEXT:   dead [[GLOBAL_LOAD_DWORD3:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[GLOBAL_LOAD_DWORD2]], 0, 0, implicit $exec
47  ; CHECK-NEXT:   dead [[GLOBAL_LOAD_DWORD4:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF4]], 0, 0, implicit $exec
48  ; CHECK-NEXT:   dead [[GLOBAL_LOAD_DWORD5:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF5]], 0, 0, implicit $exec
49  ; CHECK-NEXT:   [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
50  ; CHECK-NEXT:   [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
51  ; CHECK-NEXT:   [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
52  ; CHECK-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
53  ; CHECK-NEXT:   [[V_LSHLREV_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64_e64 2, [[DEF2]], implicit $exec
54  ; CHECK-NEXT:   [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
55  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF7]], implicit [[V_LSHLREV_B64_e64_]].sub0, implicit [[DEF6]], implicit [[V_MOV_B32_e32_1]]
56  ; CHECK-NEXT:   GLOBAL_STORE_DWORD [[DEF5]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec
57  ; CHECK-NEXT: {{  $}}
58  ; CHECK-NEXT: bb.1:
59  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
60  ; CHECK-NEXT: {{  $}}
61  ; CHECK-NEXT:   S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
62  ; CHECK-NEXT:   DBG_VALUE
63  ; CHECK-NEXT:   DBG_VALUE
64  ; CHECK-NEXT:   DBG_VALUE
65  ; CHECK-NEXT:   S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
66  ; CHECK-NEXT: {{  $}}
67  ; CHECK-NEXT: bb.2:
68  ; CHECK-NEXT:   S_NOP 0, implicit [[COPY]]
69  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF8]]
70  ; CHECK-NEXT:   S_ENDPGM 0
71  bb.0:
72    liveins: $vgpr0
73
74    %0:vgpr_32 = COPY $vgpr0
75    %1:vreg_64 = IMPLICIT_DEF
76    %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, implicit $exec
77    %3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, implicit $exec
78    undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec
79    %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
80    %5:vreg_64 = COPY %2
81    undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $mode, implicit $exec
82    %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $mode, implicit $exec
83    %7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, implicit $exec
84    %8:vreg_64 = IMPLICIT_DEF
85    %9:vreg_64 = IMPLICIT_DEF
86    %10:vreg_64 = IMPLICIT_DEF
87    undef %11.sub1:vreg_64 = IMPLICIT_DEF
88    %12:vgpr_32 = IMPLICIT_DEF
89    %13:vgpr_32 = IMPLICIT_DEF
90    %14:vreg_64 = IMPLICIT_DEF
91    %15:vreg_64 = IMPLICIT_DEF
92    %16:vgpr_32 = IMPLICIT_DEF
93    %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
94    %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
95    undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $mode, implicit $exec
96    %19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $mode, implicit $exec
97    GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, implicit $exec
98    %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, implicit $exec
99    %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, implicit $exec
100    %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, implicit $exec
101    %21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, implicit $exec
102    %22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, implicit $exec
103    %23:vreg_64 = V_LSHLREV_B64_e64 2, %8, implicit $exec
104    S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17
105    GLOBAL_STORE_DWORD %15, %18, 0, 0, implicit $exec
106
107  bb.1:
108    S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
109    DBG_VALUE
110    DBG_VALUE
111    DBG_VALUE
112    S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
113
114  bb.2:
115    S_NOP 0, implicit %0
116    S_NOP 0, implicit %16
117    S_ENDPGM 0
118
119...
120