xref: /llvm-project/llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll (revision b853988e0dfa5d18a9c486d7701c82fe79b601f3)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -mtriple=amdgcn-- -S -amdgpu-rewrite-undef-for-phi %s | FileCheck -check-prefix=OPT %s
3; RUN: opt -mtriple=amdgcn-- -S -passes=amdgpu-rewrite-undef-for-phi %s | FileCheck -check-prefix=OPT %s
4
5define amdgpu_ps float @basic(float inreg %c, i32 %x) #0 {
6; OPT-LABEL: @basic(
7; OPT-NEXT:  entry:
8; OPT-NEXT:    [[CC:%.*]] = icmp slt i32 [[X:%.*]], 0
9; OPT-NEXT:    br i1 [[CC]], label [[IF:%.*]], label [[END:%.*]]
10; OPT:       if:
11; OPT-NEXT:    br label [[END]]
12; OPT:       end:
13; OPT-NEXT:    ret float [[C:%.*]]
14;
15entry:
16  %cc = icmp slt i32 %x, 0
17  br i1 %cc, label %if, label %end
18
19if:
20  br label %end
21
22end:
23  %c2 = phi float [ undef, %if ], [ %c, %entry ]
24  ret float %c2
25}
26
27define amdgpu_ps float @with_uniform_region_inside(float inreg %c, i32 inreg %d, i32 %x) #0 {
28; OPT-LABEL: @with_uniform_region_inside(
29; OPT-NEXT:  entry:
30; OPT-NEXT:    [[CC:%.*]] = icmp slt i32 [[X:%.*]], 0
31; OPT-NEXT:    br i1 [[CC]], label [[IF:%.*]], label [[END:%.*]]
32; OPT:       if:
33; OPT-NEXT:    [[CC2:%.*]] = icmp slt i32 [[D:%.*]], 0
34; OPT-NEXT:    br i1 [[CC2]], label [[BB2:%.*]], label [[BB3:%.*]]
35; OPT:       bb2:
36; OPT-NEXT:    br label [[END]]
37; OPT:       bb3:
38; OPT-NEXT:    [[CC3:%.*]] = icmp slt i32 [[D]], 2
39; OPT-NEXT:    br i1 [[CC3]], label [[BB4:%.*]], label [[END]]
40; OPT:       bb4:
41; OPT-NEXT:    br label [[END]]
42; OPT:       end:
43; OPT-NEXT:    ret float [[C:%.*]]
44;
45entry:
46  %cc = icmp slt i32 %x, 0
47  br i1 %cc, label %if, label %end
48
49if:
50  %cc2 = icmp slt i32 %d, 0
51  br i1 %cc2, label %bb2, label %bb3
52
53bb2:
54  br label %end
55
56bb3:
57  %cc3 = icmp slt i32 %d, 2
58  br i1 %cc3, label %bb4, label %end
59
60bb4:
61  br label %end
62
63end:
64  %c2 = phi float [ undef, %bb2 ], [ %c, %bb3 ], [ undef, %bb4 ], [ %c, %entry ]
65  ret float %c2
66}
67
68define amdgpu_ps float @exclude_backedge(float inreg %c, i32 %x) #0 {
69; OPT-LABEL: @exclude_backedge(
70; OPT-NEXT:  entry:
71; OPT-NEXT:    [[CC:%.*]] = icmp slt i32 [[X:%.*]], 0
72; OPT-NEXT:    br i1 [[CC]], label [[END:%.*]], label [[LOOP:%.*]]
73; OPT:       loop:
74; OPT-NEXT:    [[IND:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ]
75; OPT-NEXT:    [[C2:%.*]] = phi float [ [[C:%.*]], [[ENTRY]] ], [ undef, [[LOOP]] ]
76; OPT-NEXT:    [[INC]] = add i32 [[IND]], 1
77; OPT-NEXT:    [[LOOP_CC:%.*]] = icmp slt i32 [[INC]], 5
78; OPT-NEXT:    br i1 [[LOOP_CC]], label [[LOOP]], label [[LOOP_END:%.*]]
79; OPT:       loop_end:
80; OPT-NEXT:    br label [[END]]
81; OPT:       end:
82; OPT-NEXT:    [[R:%.*]] = phi float [ [[C2]], [[LOOP_END]] ], [ [[C]], [[ENTRY]] ]
83; OPT-NEXT:    ret float [[R]]
84;
85entry:
86  %cc = icmp slt i32 %x, 0
87  br i1 %cc, label %end, label %loop
88
89loop:
90  %ind = phi i32 [ 0, %entry ], [ %inc, %loop ]
91  %c2 = phi float [ %c, %entry ], [ undef, %loop ]
92  %inc = add i32 %ind, 1
93  %loop_cc = icmp slt i32 %inc, 5
94  br i1 %loop_cc, label %loop, label %loop_end
95
96loop_end:
97  br label %end
98
99end:
100  %r = phi float [ %c2, %loop_end ], [ %c, %entry ]
101  ret float %r
102}
103
104attributes #0 = { nounwind noinline }
105