1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s 3--- | 4 define void @test_vreg_96_w64() !dbg !5 { 5 entry: 6 call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11 7 unreachable, !dbg !11 8 } 9 10 declare void @llvm.dbg.value(metadata, metadata, metadata) #0 11 12 attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 13 14 !llvm.dbg.cu = !{!0} 15 !llvm.mir.debugify = !{!2, !3} 16 !llvm.debugify = !{!3, !3} 17 !llvm.module.flags = !{!4} 18 19 !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) 20 !1 = !DIFile(filename: "t.mir", directory: "/") 21 !2 = !{i32 6} 22 !3 = !{i32 1} 23 !4 = !{i32 2, !"Debug Info Version", i32 3} 24 !5 = distinct !DISubprogram(name: "test_vreg_96_w64", linkageName: "test_vreg_96_w64", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) 25 !6 = !DISubroutineType(types: !7) 26 !7 = !{} 27 !8 = !{!9} 28 !9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10) 29 !10 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) 30 !11 = !DILocation(line: 1, column: 1, scope: !5) 31 32... 33--- 34name: test_vreg_96_w64 35body: | 36 bb.0: 37 ; CHECK-LABEL: name: test_vreg_96_w64 38 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec, debug-location !11 39 ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_]].sub0, $noreg, !9, !DIExpression(), debug-location !11 40 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5) 41 ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_]].sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5) 42 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]], debug-location !DILocation(line: 3, column: 1, scope: !5) 43 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5) 44 ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_1]].sub0, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5) 45 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5) 46 ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_1]].sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5) 47 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]], debug-location !DILocation(line: 6, column: 1, scope: !5) 48 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5) 49 ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_2]], $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5) 50 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5) 51 ; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_2]], $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5) 52 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]], debug-location !DILocation(line: 6, column: 1, scope: !5) 53 undef %0.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec, debug-location !11 54 DBG_VALUE %0.sub0, $noreg, !9, !DIExpression(), debug-location !11 55 %0.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5) 56 DBG_VALUE %0.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5) 57 S_NOP 0, implicit %0.sub0_sub1, debug-location !DILocation(line: 3, column: 1, scope: !5) 58 59 undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5) 60 DBG_VALUE %1.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5) 61 %1.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5) 62 DBG_VALUE %1.sub2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5) 63 S_NOP 0, implicit %1.sub1_sub2, debug-location !DILocation(line: 6, column: 1, scope: !5) 64 65 undef %2.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5) 66 DBG_VALUE %2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5) 67 %2.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5) 68 DBG_VALUE %2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5) 69 S_NOP 0, implicit %2.sub1_sub2, debug-location !DILocation(line: 6, column: 1, scope: !5) 70... 71 72