xref: /llvm-project/llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir (revision ac0f64f06d67a93817ccd9a3c529ad40920115c9)
1# RUN: not llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs=0 -start-before=greedy,1 -stop-after=virtregrewriter,2 %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
2# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -start-before=greedy,1 -stop-after=virtregrewriter,2 %s -o /dev/null 2>&1 | FileCheck -check-prefixes=ERR,VERIFIER %s
3
4# FIXME: We should not produce a verifier error after erroring
5
6# ERR: error: inline assembly requires more registers than available
7# VERIFIER: *** Bad machine code: Using an undefined physical register ***
8
9# This testcase cannot be compiled with the enforced register
10# budget. Previously, tryLastChanceRecoloring would assert here. It
11# was attempting to recolor a superregister with an overlapping
12# subregister over the same range.
13
14--- |
15  define void @foo() #0 {
16    ret void
17  }
18
19  attributes #0 = { "amdgpu-waves-per-eu"="8,8" }
20
21...
22---
23name:            foo
24tracksRegLiveness: true
25registers:
26  - { id: 0, class: vgpr_32 }
27  - { id: 1, class: vgpr_32 }
28  - { id: 2, class: vreg_512 }
29  - { id: 3, class: vreg_256 }
30  - { id: 4, class: vreg_128 }
31  - { id: 5, class: vreg_96 }
32  - { id: 6, class: vreg_96 }
33  - { id: 7, class: vreg_512 }
34  - { id: 8, class: vreg_256 }
35  - { id: 9, class: vreg_128 }
36  - { id: 10, class: vreg_96 }
37  - { id: 11, class: vreg_96 }
38  - { id: 12, class: sreg_64 }
39  - { id: 13, class: sgpr_64 }
40  - { id: 14, class: vgpr_32 }
41machineFunctionInfo:
42  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
43  frameOffsetReg:  '$sgpr33'
44  stackPtrOffsetReg: '$sgpr32'
45body:             |
46  bb.0:
47
48    INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $agpr0
49    %14:vgpr_32 = COPY killed $agpr0
50    INLINEASM &"; def $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 11534346 /* regdef:VReg_512 */, def %7, 10158090 /* regdef:VReg_256 */, def %8, 4784138 /* regdef:VReg_128 */, def %9, 3670026 /* regdef:VReg_96 */, def %10, 3670026 /* regdef:VReg_96 */, def %11
51    INLINEASM &"; clobber", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, 12 /* clobber */, implicit-def dead early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
52    INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 11534345 /* reguse:VReg_512 */, %7
53    INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10158089 /* reguse:VReg_256 */, %8
54    INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4784137 /* reguse:VReg_128 */, %9
55    INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3670025 /* reguse:VReg_96 */, %10
56    INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3670025 /* reguse:VReg_96 */, %11
57    $agpr1 = COPY %14
58    INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 9 /* reguse */, killed $agpr1
59    SI_RETURN
60
61...
62