xref: /llvm-project/llvm/test/CodeGen/AMDGPU/pv-packing.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s
3
4define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
5; CHECK-LABEL: main:
6; CHECK:       ; %bb.0: ; %main_body
7; CHECK-NEXT:    CALL_FS
8; CHECK-NEXT:    ALU 11, @4, KC0[CB0:0-32], KC1[]
9; CHECK-NEXT:    EXPORT T0.X___
10; CHECK-NEXT:    CF_END
11; CHECK-NEXT:    ALU clause starting at 4:
12; CHECK-NEXT:     DOT4 T0.X, KC0[0].X, KC0[0].X,
13; CHECK-NEXT:     DOT4 T0.Y (MASKED), KC0[0].Y, KC0[0].Y,
14; CHECK-NEXT:     DOT4 T0.Z (MASKED), KC0[0].Z, KC0[0].Z,
15; CHECK-NEXT:     DOT4 * T0.W (MASKED), KC0[0].W, KC0[0].W,
16; CHECK-NEXT:     MULADD_IEEE T2.X, T1.X, T2.X, T3.X,
17; CHECK-NEXT:     MULADD_IEEE T0.Y, T1.Y, T2.Y, T3.Y,
18; CHECK-NEXT:     MULADD_IEEE T0.Z, T1.Z, T2.Z, T3.Z,
19; CHECK-NEXT:     MULADD_IEEE * T0.W, PV.X, PV.X, T1.X, BS:VEC_120/SCL_212
20; CHECK-NEXT:     DOT4 T0.X, T2.X, KC0[1].X,
21; CHECK-NEXT:     DOT4 T0.Y (MASKED), T0.Y, KC0[1].Y,
22; CHECK-NEXT:     DOT4 T0.Z (MASKED), T0.Z, KC0[1].Z,
23; CHECK-NEXT:     DOT4 * T0.W (MASKED), T0.W, KC0[1].W,
24main_body:
25  %0 = extractelement <4 x float> %reg1, i32 0
26  %1 = extractelement <4 x float> %reg1, i32 1
27  %2 = extractelement <4 x float> %reg1, i32 2
28  %3 = extractelement <4 x float> %reg2, i32 0
29  %4 = extractelement <4 x float> %reg2, i32 1
30  %5 = extractelement <4 x float> %reg2, i32 2
31  %6 = extractelement <4 x float> %reg3, i32 0
32  %7 = extractelement <4 x float> %reg3, i32 1
33  %8 = extractelement <4 x float> %reg3, i32 2
34  %9 = load <4 x float>, ptr addrspace(8) null
35  %10 = load <4 x float>, ptr addrspace(8) getelementptr ([1024 x <4 x float>], ptr addrspace(8) null, i64 0, i32 1)
36  %11 = call float @llvm.r600.dot4(<4 x float> %9, <4 x float> %9)
37  %12 = fmul float %0, %3
38  %13 = fadd float %12, %6
39  %14 = fmul float %1, %4
40  %15 = fadd float %14, %7
41  %16 = fmul float %2, %5
42  %17 = fadd float %16, %8
43  %18 = fmul float %11, %11
44  %19 = fadd float %18, %0
45  %20 = insertelement <4 x float> undef, float %13, i32 0
46  %21 = insertelement <4 x float> %20, float %15, i32 1
47  %22 = insertelement <4 x float> %21, float %17, i32 2
48  %23 = insertelement <4 x float> %22, float %19, i32 3
49  %24 = call float @llvm.r600.dot4(<4 x float> %23, <4 x float> %10)
50  %25 = insertelement <4 x float> undef, float %24, i32 0
51  call void @llvm.r600.store.swizzle(<4 x float> %25, i32 0, i32 2)
52  ret void
53}
54
55; Function Attrs: readnone
56declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1
57
58
59declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
60
61attributes #1 = { readnone }
62